PROCESSOR TECHNOLOGY CORPORATION
Sol THEORY OF OPERATION SECTION VIII
The A-to-B jumper is installed when the 8080A or 8080A-1 CPU
is used in the Sol. Note that the output (
φ
2) on pin 11 of NAND gate
U91 is low only when the output on pin 3 of NOR gate U91 is high.
(This section in U91 is actually a two-input NAND gate which is func-
tionally the same as a two-input NOR gate.) Pin 3 of U91, with the
A-to-B jumper in, is high when either the second (B) or third (C) U90
stage is at zero. As shown in Figure 8-1, this occurs between the
sixth and tenth DOT CLOCKS, or 280 nsec (4 x 70 nsec), for 2.04 MHz
operation. For 2.863 MHz, it occurs between the fifth and eighth
DOT CLOCKS for 210 nsec. The section of NAND gate U91 with its out-
put on pin 11 inverts the output on pin 3 of U91 and introduces a
slight delay to insure there is no overlap between
φ
1 and
φ
2.
With the A-to-B jumper out, pin II of U91 is low only when
the second stage (B) of U90 is at zero. At 2.386 MHz, this occurs
between the fifth and eighth DOT CLOCKS for 210 nsec. This configu-
ration is used for the 8080A-2 CPU.
In summary, we have two non-overlapping pulse trains which
represent the 01 and 02 clocks required by the 8080 CPU, and the
pulse widths of these two clocks vary with frequency as follows:
FREQUENCY
φ
1 PULSE WIDTH
φ
2 PULSE WIDTH CPU
2.045 MHz 140 nsec 280 nsec 8080A
2.386 MHz 70 nsec 210 nsec 8080A-2
2.863 MHz 70 nsec 210 nsec 8080A-1
φ
1 and
φ
2 are applied to S-100 Bus pins 25 and 24 respectively
through inverters (U92) and bus drivers (U77). They are also capaci-
tively coupled to pins 2 and 4 respectively of driver U104, the phase
clock conditioner.
An additional clock, called CLOCK, is taken from pin 8 of
NAND gate U91. It occurs 70 nsec after
φ
2. It is used on the Sol-PC
and is also made available on S-100 Bus pin 49 as a general 2.04,
2.38 or 2.86 MHz clock signal.
Three J-K flip-flops (U63 and 64) are used to synchronize the
READY, RESET and HOLD inputs to the CPU. All three are connected as
D-type flip-flops so that their outputs follow their inputs on the
low-to-high transition of the clock. The READY flip-flop input on
pins 2 and 3 of one section in U63 is either PRDY or XRDY from the
S-100 Bus; these are normally pulled high by R34 and R12 respectively.
S-100 Bus signal !PRESET, which is normally pulled high by R55, inputs
the RESET flip-flop, the other section of U63. The HOLD flip-flop
(U64) input is !P_HOLD, normally pulled high by R56, from the S-100
Bus. Pull up resistors R51, R50 and R53 insure that the high states
of these three flip-flops are adequate for the CPU.
VIII-10
Summary of Contents for Sol-PC
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