PROCESSOR TECHNOLOGY CORPORATION
Sol THEORY OF OPERATION SECTION VIII
Diode D7, Cl5 and R18 make up the POC (power on clear) cir-
cuit. When power is applied, Cl5 starts to charge slowly until it
reaches the threshold on pin 6 of U46, a Schmitt trigger. (By this
time the logic and 5 volt supply have stabilized. ) When the thresh-
old is reached, pin 1 of U46 suddenly goes low. The resulting output
on pin 8 of inverter U92 is initially low and then rapidly goes high.
This signal is passed through a section of U77, a permanently enabled
noninverting tri-state driver, as !POC to S-100 Bus pin 99. It is
also inverted in a section of U45 to become POC.
The output on pin 8 of U92 is also connected to pin 15 of
U63. Thus, pin 9 (RESET) of U63 is high to start the CPU in the
reset condition when the Sol is initially turned on.
When !POC goes high, the RESET flip-flop section of U63 is
free to clock. Assuming !PRESET is not active, it will change state
on the first CLOCK transition. The resulting high on pins 10 and 5
of U63 cause pin 7 (READY) of U63 to go low to place the CPU in the
not ready or wait state. This state is subsequently removed on the
CLOCK transition following the transition which removed the low from
pin 5 of U63. This helps prevent the CPU from starting in a crash
condition.
The HOLD flip-flop (U64), however, is not affected by the POC
circuit, and was clocked to a low on pin 7 well before the RESET and
READY signals became active.
Operation of the POC circuit can also be initiated, without
turning the power off, by a keyboard restart signal on pin 13 of J3
or by closing S1-1 if the N-P jumper is in. In either case, C15 is
discharged through R58 and then allowed to recharge after !KBD_RESTART
is removed or S1-1 is opened.
!POC also resets all stages of D flip-flop U76 (the phantom
start-up circuit) to zero. On initial start-up, the CPU performs
four fetch machine cycles (refer to Intel® 8080 Microcomputer Sys-
tems User's Manual) in accordance with program instructions. For
each fetch, the CPU outputs a DBIN on pin 17. U76, connected as a
four-stage shift register, is clocked by the inverted DBIN signal on
pin 3 of NOR gate U46. Thus, !PHANTOM, on S-100 Bus pin 67, is active
low (assuming the F-to-G jumper is in) for the first four fetches or
machine cycles. After the fourth DBIN, !PHANTOM goes high. !PHANTOM
is used to 1) disable any memory addressed in Page 0 that has Proces-
sor Technology’s exclusive “Phantom Disable” feature and 2) cause the
Sol program memory (ROM), which normally responds to Page C0 (hex) to
respond to Page 00 (hex). The second function is discussed in Para-
graph 8.5.2.
VIII-12
Summary of Contents for Sol-PC
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