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PROCESSOR TECHNOLOGY CORPORATION

Sol THEORY OF OPERATION SECTION VIII

The System RAM consists of eight 1K by 1 bit static memory
chips, U3 through U10, and it is assigned addresses C800-CBFF (hex).
When the CPU wants to write data into memory, it addresses the System
RAM on ADR0-15. ADR0-4 select the row inside the RAM chips, ADR5-9
select the column, and ADR10-15 select the page (in this case Page
C8, hex). Page selection enables the eight RAM chips on pin 13.
For a read operation, MWRITE on S-1OO Bus pin 68 is low, and the re-
sulting high on pin 3 (WE) of the RAM chips keeps them in the read
mode. Thus, data on the Bidirectional Data Bus is read into the
PRAM'S on their D1 (pin 11) inputs. MWRITE is high, however, during
the time the CPU wants to write data into memory. In this case, pin
3 of the RAM's is low to enable them to accept data from the Bidirec-
tional Data Bus.

The ROM is also addressed on ADR0-15 as is the System RAM.
Since there can be two pages, however, two enable lines (one for Page
C0, hex, and the other for C4, hex) are provided. The C0 and C4
enables are connected to pins A6 and A5 respectively of J5, the Per-
sonality Module connector. Unlike the RAM, the ROM can only read
data into the CPU, so the previously discussed MWRITE signal is not
needed. Data out of the ROM is output on the Internal Data Bus on
pins A3, A4 and B5-10 of J5.

ADR10-15 are input to the Address Page and Port Decoder (U34,
35, 36 and their associated logic). U34 (Address Page), U35 (Output
Port) and U36 (Input Port) are 3-to-8 line decoders which have three
enable inputs (G1, G2A and G2B). G1 must be high and both G2A and B
must be low in order to obtain an active output.

Let's look at the Address Page Decoder, U34, first. It must
be able to decode four pages: C0 and C4 (ROM), C8 (System RAM) and
CC (Display RAM). (Note that these are the hexadecimal digits of the
six high order address bits, ADR10-15).

The high order four bits (ADR12-15) must be 1100 (C, hex) in
all cases by virtue of the U22 exclusive OR logic. If they are not,
the G1 enable on U34 is low to disable that decoder. Bits ADR10 and
11 (The A and B inputs to U34) are the high order bits of the second
hexadecimal digit which must be 00 (0, hex), 01 (4, hex), 10 (8, hex)
or 11 (12, hex) if U34 is to have an active output. For C0, pin 11
of U34 is active (low); for C4, pin 10 is active; for C8 pin 9 is ac-
tive; and for CC pin 7 is active. These outputs are applied to the
appropriate memories and also provide the MEM_SEL signal on pin 6 of
one section in U23. (This section is actually a 4-input NAND gate
which is functionally the same as a 4-input NOR gate.)

Note that the U22 logic input with ADR14 and 15 is also con-
nected to !PHANTOM. When this signal is active (low), the output on
pins 3 and 11 will be low to disable U34 when ADR12-15 represent a
C. If Page 0 is addressed, however, pins 3 and 11 of U22 are high,
and this, coupled with lows on ADR10-13, are decoded by U34 as an
active output on pin 11. The ROM will consequently respond to ad-
dresses in Page 0 and C0 (hex) as long as !PHANTOM is active.

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