PROCESSOR TECHNOLOGY CORPORATION
Sol THEORY OF OPERATION SECTION VIII
PXDR on pin 16 of J2 is supplied by the external device. It
indicates the device is ready to receive data. !PXDR is buffered to
INT2 and will effect the transfer of data to the Internal Data Bus
during the status input to the CPU. !PXDR is analogous to the pre-
viously discussed PIAK signal.
Sense Switches S2-1 through 8 are driven by !PORT_IN_FF when
it is low. Thus, the DIO lines connected to closed switches are
driven low, and those connected to open switches are pulled high.
U97 (a 4-bit D-type register) and one section of U52 (a J-!K
flip-flop connected as a D flip-flop) latch five bits of data on
D103-7 when !PORT_OUT_FA goes active. These bits, which supply the
indicated outputs, control conditions in both the PP and CDI. With
respect to the PP, PIE enables parallel input, and PUS selects the
parallel device for the transfer. The data in these two latches re-
mains until either a new word is read out or POC goes active.
Also during !PORT_OUT_FA, the keyboard flag is reported.
!KEYBOARD_DATA_READY on pin 3 of J3 is a low going pulse 1 to 10 usec
in duration. It is applied to pin 13 of J-!K flip-flop U70. Some
time after pin 13 of U70 goes low, but before 500 nsec, U70 is set
by
φ
2 and pin 10 goes low. This low is buffered through U71 to INT0
to indicate the keyboard is ready to send data. Reset of U70 occurs
with a POC or by !PORT_IN_FC. The latter occurs when data is accepted
from the keyboard.
The other half of flip-flop U52, with its output on pin 6,
latches one bit of status, D104, when !PORT_OUT_F8 is active. Its
output is applied to pin 5 of one operational amplifier section in
U56 to become the SRTS (request to send) signal on pin 4 of J1, the
SDI connector.
The SDI/UART centers around a UART, U51. The UART transmis-
sion conditions (parity, word length and stop bits) are determined by
the settings of S4-1 through 5. (Refer to Paragraphs 7.5.8 through
7.5.10 in Section VII for descriptions of the switch settings and
their effect on transmission.
Data destined to leave Sol through the SDI/UART enters the
UART on its TI1-6 inputs from the Bidirectional Data Bus when TBRL
(pin 23) is low; that is, when !PORT_OUT_F9 goes active. Circuitry
within the UART serializes the input data, which is in parallel form,
and outputs it on pin 25 at a rate determined by the clock on pin 40.
The binary states at pin 25 are low for a zero and high for a one.
Assuming Sol is not in local operation ("off line"), the output on
pin 25 of the UART is applied to pins 2 and 11 of J1 via two gates in
U55 and the other half of U56.
VIII-19
Summary of Contents for Sol-PC
Page 35: ......
Page 89: ......
Page 90: ......
Page 91: ......
Page 92: ......
Page 93: ......
Page 94: ......
Page 95: ......
Page 96: ......
Page 97: ......
Page 98: ......
Page 99: ......
Page 100: ......
Page 101: ......
Page 102: ......
Page 103: ......
Page 104: ......
Page 105: ......
Page 106: ......
Page 107: ......
Page 108: ......
Page 151: ...VIII 11...
Page 167: ...VIII 27...
Page 186: ......
Page 187: ...SECTION IX SOFTWARE Sol TERMINAL COMPUTERTM Processor Technology...
Page 191: ......
Page 197: ......
Page 223: ......
Page 224: ......
Page 225: ......
Page 226: ......
Page 227: ......
Page 228: ......
Page 229: ......
Page 230: ......
Page 231: ......
Page 232: ......
Page 233: ......
Page 234: ......
Page 235: ......
Page 236: ......
Page 237: ......
Page 238: ......
Page 239: ......
Page 240: ......
Page 241: ......
Page 242: ......
Page 243: ......
Page 244: ......
Page 245: ......
Page 246: ......
Page 247: ......
Page 248: ......
Page 249: ......
Page 250: ......
Page 251: ......
Page 252: ......
Page 253: ......
Page 254: ......
Page 255: ......
Page 256: ......
Page 257: ......
Page 258: ......
Page 259: ......
Page 260: ......
Page 261: ......
Page 262: ......
Page 263: ......
Page 264: ......
Page 265: ......
Page 266: ......
Page 267: ......
Page 268: ......
Page 269: ......
Page 270: ......
Page 271: ......
Page 272: ......
Page 273: ......
Page 274: ......
Page 275: ......
Page 276: ......
Page 277: ......
Page 278: ......
Page 279: ......
Page 280: ......
Page 281: ......
Page 282: ......
Page 283: ......
Page 284: ......