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PROCESSOR TECHNOLOGY CORPORATION

Sol THEORY OF OPERATION SECTION VIII

2 respectively. This circuit thus generates a symmetrical two phase

clock, with each phase having a 6 usec period with a 1.5 usec nega-
tive going pulse.

1 advances the cascaded ripple counter, U5 and 6, in the

Column Scanner circuit (U5, U6, NAND gates U4 and decoders U17 and

U21). U6 divides

1 by two on each advance. The output on pin 12 is

consequently a square wave with a 12 usec period, the output on pin 9
is a square wave with a 24 usec period, and so on to pin 11 which has
a 96 usec period. The output on pin 11 is then divided by two in U5
to provide 192, 384, 760 and 1536 usec periods. We will call these
Clock_1 for the 12 usec period, Clock_2 for the 24 usec period, Clock_
4 for the 48 usec period, and so on from Clock_8, _16, _32, _64 and _128.

Clocks_16, _32 and _64 are applied to the A, B and C inputs of
binary-to-decimal decoders U17 and U21. In order for these decoders
to yield outputs, their D inputs (pin 12) must be low. U4 is used to
enable one or the other of these inputs, with Clock 128 being the de-
termining factor. When Clock_128 is low, U17 is selected through U4

when

1 is high at pin 4 of U4. U21 is selected when Clock_128 is

high and

1 is high at pin 13 of U4. By AND’ing

1 and Clock_128,

neither decoder is selected when

1 is low, the time U5 and U6 count.

During this time false binary signals can appear on the outputs of U5
and 6.

The net effect is that only one of the 15 outputs from U17
and 21 will be low, and this low advances on each count advance. The
low outputs of U17 and 21 drive the column lines in the key switch
matrix.

Clocks_1 through _8 are connected to analog multiplexers U19
and U22. Only one channel from input to output is connected at one
time. Note that Clock_8 and !Clock_8 from U6 enable U19 and U22 re-
spectively. U19 and U22 (the Row Scanner) thus scan through the 16
rows in the sequence indicated by the numbers contained within the
"boxes" of the key switch matrix. An entire scan of the rows is made
before the next column is selected by U17 and 21.

We now have U17 and U21 driving the column lines and U19 and
U22 testing each row line by connecting it to an input to the Capaci-
tance Key switch (KTC) Detector. These two inputs are normally high
at 5 volts. Within the switch matrix there is a small capacitance
connected between each column and row line; that is, there is a capa-
citance associated with each key on the keyboard. When a key is de-
pressed on the keyboard, the capacitance associated with that key in-
creases. When the column and row lines associated with that key are
selected, there is a significant voltage difference between the two
and the capacitance charges to produce a small negative going spike
at the input to the Capacitance Keyswitch Detector.

Processor Technology Sol-PC, Manual

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