5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
CFG7
DEFENSIVE PULL DOWN SITE
1: (Default) PEG Train immediately following xxRESETB de assertion
0: PEG Wait for BIOS for training
CFG4
1: DISABLED;
NO PHYSICAL DISPLAY PORT ATTACHED
TO EMBEDDED DISPLAY PORT
0: ENABLED;
AN EXTERNAL DISPLAY PORT DEVICE
IS CONNECTED TO THE EMBEDDED
DISPLAY PORT
DISPLAY PORT PRESENCE STRAP
CFG2
1: (DEFAULT)NORMAL OPERATION;
LANE# DEFINITION MATCHES
SOCKET PIN MAP DEFINITION
0: LANE REVERSAL
PCI EXPRESS STATIC LANE REVERSAL FOR ALL PEG PORTS
CFG[6:5]
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
PCIE PORT BIFURCATION STRAPS
CFG[0]: Stall reset sequence after PCU PLL
Ʉ
lock until de-asserted:
— 1 = (Default) Normal Operation; No
stall.
— 0 = Stall.
CFG[1]: Reserved configuration lane.
Ʉ
CFG[2]: PCI Express* Static x16 Lane
Ʉ
Numbering Reversal.
— 1 = Normal operation
— 0 = Lane numbers reversed.
CFG[3]: Reserved configuration lane.
Ʉ
CFG[4]: eDP enable:
Ʉ
— 1 = Disabled.
— 0 = Enabled.
CFG[6:5]: PCI Express* Bifurcation
Ʉ
— 00 = 1 x8, 2 x4 PCI Express*
— 01 = reserved
— 10 = 2 x8 PCI Express*
— 11 = 1 x16 PCI Express*
CFG[7]: PEG Training:
Ʉ
— 1 = (default) PEG Train immediately
following RESET# de assertion.
— 0 = PEG Wait for BIOS for training.
CFG[19:8]: Reserved configuration lanes.
Ʉ
TO EC
NEAR CPU
TO PCH-H
VCCST_PWRGD
CAD Note: Capacitor need to be placed
close to buffer output pin
Configuration Signals: The CFG signals have a
default value of '1' if not terminated on the board.
Refer to the appropriate platform design guide for
pull-down recommendations when a logic low is
desired.
VIDALERT#
PROCHOT#
H_PROCHOT#
VCCST_PWRGD_CPU
VCCST_PWRGD
PM_DOWN
PECI
H_SKTOCC_N
H_TDO
H_TDI
H_TMS
H_TCK
H_TRST#
H_PREQ#
H_PRDY#
CFG_RCOMP
CFG0
CFG3
CFG4
CFG5
CFG6
CFG7
H_TDO
H_TCK
H_SKTOCC_N
CFG8
SYS_PWRGD#
VCCST_PWRGD
H_PROCHOT#
CFG_1
CFG9
CFG11
CFG14
CFG15
H_TDI
H_TMS
1.05DX_VCCSTG
3.3VA
1.05V_VCCST
1.05V_VCCST
VDD3
1.05DX_VCCSTG
1.05DX_VCCSTG
6,33,54
VDD3
22,30,31,33,35,36,38,40,42,43,46,48,49,50,54,56,57,58,59,60,61
1.05V_VCCST
6,32,49,53
H_PROCHOT#
53
PCH_CPU_BCLK_R_DN
35
PCH_CPU_BCLK_R_DP
35
PCH_CPU_PCIBCLK_R_DN
35
PCH_CPU_PCIBCLK_R_DP
35
CPU_24MHZ_R_DN
35
CPU_24MHZ_R_DP
35
H_PWRGD
33
PLTRST_CPU_N
32
H_PM_SYNC
32
H_SKTOCC_N
34,38
DDR_VTT_PG_CTRL
51
H_CPU_SVIDCLK
53
H_CPU_SVIDDAT
53
H_CPU_SVIDALRT#
53
PCH_THERMTRIP#
32
PCH_PECI
32
H_PM_DOWN
32
H_PECI
46
3.3VA
30,31,32,33,36,38,49,54
ALL_SYS_PWRGD
28,31,46,53
H_PROCHOT_EC
46
VCCIO
2,6,49
H_TCK
33
H_TMS
33
H_TDO
33
H_TDI
33
H_TRST#
38
H_PREQ#
38
H_PRDY#
38
Title
Size
Document Number
R e v
Date :
Sheet
o f
6-71-N85E0-D02
D02
[04]Processor 4/7-CLK/JTAG/MISC
A3
4
69
Tuesday, April 10, 2018
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
SCHEMATIC1
Title
Size
Document Number
R e v
Date :
Sheet
o f
6-71-N85E0-D02
D02
[04]Processor 4/7-CLK/JTAG/MISC
A3
4
69
Tuesday, April 10, 2018
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
SCHEMATIC1
Title
Size
Document Number
R e v
Date :
Sheet
o f
6-71-N85E0-D02
D02
[04]Processor 4/7-CLK/JTAG/MISC
A3
4
69
Tuesday, April 10, 2018
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
SCHEMATIC1
R476
*12.1_1%_04
T179
R503
*1K_04
R471
499_1%_04
R32
56.2_1%_04
5 OF 13
?
?
?
?
U29E
CFL_H_62_INT_IP_CRB_CFLH/BGA
VIDSOUT
BH29
DDR_VTT_CNTL
BT13
VCCST_PW RGD
H13
PM_SYNC
BM34
PM_DOW N
BP31
PECI
BT34
CFG_18
BN22
PROC_TCK
BR28
CFG_19
BP22
THERMTRIP#
J31
PROC_TDO
BT28
CFG_0
BN25
PROC_TRST#
BP30
CFG_1
BN27
PROC_SELECT#
BN1
ZVM#
AT13
SKTOCC#
BR33
CFG_2
BN26
CFG_RCOMP
BT25
CFG_3
BN28
PROC_PREQ#
BL30
CFG_4
BR20
CFG_10
BT23
RESET#
BP35
CFG_5
BM20
CLK24N
D31
PROCPW RGD
BT31
CFG_11
BT22
CFG_6
BT20
BPM#_0
BR27
VIDSCK
BH32
BCLKN
A32
PCI_BCLKN
C36
BPM#_1
BT27
CFG_7
BP20
CFG_12
BM19
CLK24P
E31
CFG_8
BR23
CFG_13
BR19
BPM#_2
BM31
BCLKP
B31
PCI_BCLKP
D35
BPM#_3
BT30
PROCHOT#
BR30
CFG_9
BR22
CFG_14
BP19
RSVD2
AY13
CFG_15
BT19
RSVD1
AU13
PROC_PRDY#
BP27
CFG_16
BP23
CATERR#
BM30
PROC_TDI
BL32
MSM#
AW 13
PROC_TMS
BP28
CFG_17
BN23
VIDALERT#
BH31
R473
1K_04
T180
C738
47P_50V_NPO_04
T17
S
D
G
Q2B
MTDK3S6R
5
3
4
R474
100K_04
T181
C213
*0.1u_10V_X7R_04
T85
T182
R56
1K_04
C209
*0.1u_10V_X7R_04
T183
R55
60.4_1%_04
R475
*0402_short
C212
*0.1u_10V_X7R_04
R34
220_04
S
D
G
Q2A
MTDK3S6R
2
6
1
R57
20K_04
R448
20_1%_04
Q30
2SK3018S3
G
D
S
R472
100_04
R489
49.9_1%_04
R37
100K_04
T177
R490
51_04
R54
51_04
R53
51_04
R33
100_04
T178
T86
R449
100K_04
R504
1K_04
Sheet 4 of 69
Processor 3/6
Schematic Diagrams
Processor 3/6 B - 5
B.Schematic Diagrams
Processor 3/6
Summary of Contents for Clevo N870EP6
Page 1: ...N870EP6 N871EP6...
Page 2: ......
Page 3: ...Preface I Preface Notebook Computer N870EP6 N871EP6 Service Manual...
Page 24: ...Introduction 1 12 1 Introduction...
Page 41: ...Top A 3 A Part Lists Top Figure A 1 Top...
Page 42: ...A 4 Bottom A Part Lists Bottom Figure A 2 Bottom...
Page 43: ...Main Board A 5 A Part Lists Main Board Figure A 3 Main Board...
Page 44: ...A 6 HDD A Part Lists HDD Figure A 4 HDD...
Page 45: ...LCD A 7 A Part Lists LCD Figure A 5 LCD...
Page 46: ...A 8 A Part Lists...
