Chapter 5 Award BIOS Setup
Page: 5-12
Prox-1550 USER
′
S MANUAL
AT BUS CLOCK:
The chipset generates the ISA bus clock (ATCLK) from an internal division
of PCICLK. You can set the speed of the AT bus in terms of a fraction of
the CPU clock speed, or at the fixed speed of 7.16MHz.
L2 TAG RAM SIZE:
The system uses tag bits to determine the status of data in the L2 cache.
Set this field to match the specifications (8 or 10 bits) of the installed tag
RAM chip.
DRAM TIMING:
The value in this field depends on performance parameters of the installed
memory chips (DRAM). Do not change the value from the factory setting
unless you install new memory that has a different performance rating than
the original DRAMs.
SDRAM CAS LATENCY:
When synchronous DRAM is installed, the number of clock cycles of CAS
latency depends on the DRAM timing. Do not reset this field from the
default value specified by the system designer.
PIPELINED FUNCTION:
When Enabled, the controller signals the CPU for a new memory address
before all data transfers for the current cycles are complete, resulting in
faster performance.
DRAM DATA INTEGRITY MODE:
Select Parity or ECC (error-correcting code), according to the type of
installed DRAM. The available choices are Disabled, ECC, Parity.
MEMORY HOLE AT 15M-16M:
This item allows you to reserve a certain space in memory for ISA cards for
better performance. This memory must be mapped into the memory space
below 16MB. The choices are enabled and disabled to set the support of
memory hole.
Summary of Contents for ProX-1550
Page 1: ...USER S MANUAL ...
Page 60: ...Chapter 3 Software Configuration Prox 1550 USER S MANUAL Page 3 11 ...
Page 64: ...Chapter 4 Green PC Function Page 4 4 Prox 1550 USER S MANUAL ...
Page 92: ...Chapter 5 Award BIOS Setup Page 5 28 Prox 1550 USER S MANUAL ...
Page 98: ...Appendix B Technical Summary Page B 2 Prox 1550 USER S MANUAL BLOCK DIAGRAM ...
