Chapter 5 Award BIOS Setup
Prox-1550 USER
′
S MANUAL
Page: 5-13
HOST READ DRAM COMMAND MODE:
This item allows you to select the type of Host Read DRAM Command
Mode. The choice are: Syn., and Bypass.
ISA LINE BUFFER:
The PCI to ISA Bridge has an 8 byte bi-directional line buffer for ISA or
DMA bus master memory reads from or writes to the PCI bus. When
Enabled, an ISA or DMA bus master can pre-fetch two double words to the
line buffer for a read cycle.
PASSIVE RELEASE:
When Enabled, CPU to PCI bus accesses is allowed during passive release.
Otherwise, the arbiter only accepts another PCI master access to local
DRAM.
DELAY TRANSACTION:
The chipset has an embedded 32-bit posted write buffer to support delay
transactions cycles. Select Enabled to support compliance with PCI
specification version 2.1.
PRIMARY FRAME BUFFER:
Select a size for the PCI frame buffer. The size of the buffer should not
impinge on local memory.
VGA FRAME BUFFER:
When enabled, a fixed VGA frame buffer from A000h to BFFFh and a
CPU-to-PCI write buffer are implemented.
DATA MERGE:
This field controls the word-merge feature for frame buffer cycles. When
enabled, this controller checks the eight CPU Byte Enable signals to
determine if data words read from the PCI bus by the CPU can be merged.
IO CHANNEL CHECK NMI:
This field enable or disable IO channel check NMI. Before selecting this
function, the user should check first that NMI function is enabled as
described in chapter 2 (Reset/NMI/Clear Watchdog).
Summary of Contents for ProX-1550
Page 1: ...USER S MANUAL ...
Page 60: ...Chapter 3 Software Configuration Prox 1550 USER S MANUAL Page 3 11 ...
Page 64: ...Chapter 4 Green PC Function Page 4 4 Prox 1550 USER S MANUAL ...
Page 92: ...Chapter 5 Award BIOS Setup Page 5 28 Prox 1550 USER S MANUAL ...
Page 98: ...Appendix B Technical Summary Page B 2 Prox 1550 USER S MANUAL BLOCK DIAGRAM ...
