14
Features
General
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Feature selection via special function register
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Simultaneous reception of TTX, VPS, PDC, and WSS (line 23)
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Supply Voltage 2.5 and 3.3 V
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ROM version package P-SDIP 52, P-MQFP64
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Romless version package P-MQFP100,P-LCC84
External Crystal and Programmable clock speed
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Single external 6MHz crystal, all necessary clocks are generated internally
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CPU clock speed selectable via special function registers.
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Normal Mode 33.33 Mhz CPU clock, Power Save mode 8.33 Mhz
Microcontroller Features
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8bit 8051 instruction set compatible CPU.
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33.33-MHz internal clock (max.)
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0.36
0
ms (min.) instruction cycle
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Two 16-bit timers
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Watchdog timer
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Capture compare timer for infrared remote control decoding
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Pulse width modulation unit (2 channels 14 bit, 6 channels 8 bit)
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ADC (4 channels, 8 bit)
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UART
Memory
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Non-multiplexed 8-bit data and 16 20-bit address bus (ROMless Version)
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Memory banking up to 1Mbyte (Romless version)
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Up to 128 Kilobyte on Chip Program ROM
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Eight 16-bit data pointer registers (DPTR)
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256-bytes on-chip Processor Internal RAM (IRAM)
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128bytes extended stack memory.
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Display RAM and TXT/VPS/PDC/WSS-Acquisition-Buffer directly accessible via MOVX
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UP to 16KByte on Chip Extended RAM(XRAM) consisting of;
- 1 Kilobyte on-chip ACQ-buffer-RAM (access via MOVX)
- 1 Kilobyte on-chip extended-RAM (XRAM, access via MOVX) for user software
- 3 Kilobyte Display Memory
Display Features
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ROM Character Set Supports all East and West European Languages in single device
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Mosaic Graphic Character Set
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Parallel Display Attributes
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Single/Double Width/Height of Characters
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Variable Flash Rate
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Programmable Screen Size (25 Rows x 33...64 Columns)
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Flexible Character Matrixes (HxV) 12 x 9...16
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Up to 256 Dynamical Redefinable Characters in standard mode; 1024 Dynamical
Redefinable Characters in Enhanced Mode
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CLUT with up to 4096 color combinations
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Up to 16 Colors per DRCS Character
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One out of Eight Colors for Foreground and Background Colors for 1-bit DRCS and ROM Characters
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Shadowing
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Contrast Reduction
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Pixel by Pixel Shiftable Cursor With up to 4 Different Colors
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Support of Progressive Scan and 100 Hz.
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3 X 4Bits RGB-DACs On-Chip
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Free Programmable Pixel Clock from 10 MHZ to 32MHz
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Pixel Clock Independent from CPU Clock
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Multinorm H/V-Display Synchronization in Master or Slave Mode
Acquisition Features
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Multistandard Digital Data Slicer
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Parallel Multi-norm Slicing (TTX, VPS, WSS, CC, G+)
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Four Different Framing Codes Available
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Data Caption only Limited by available Memory
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Programmable VBI-buffer
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Full Channel Data Slicing Supported
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Fully Digital Signal Processing
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Noise Measurement and Controlled Noise Compensation
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Attenuation Measurement and Compensation
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Group Delay Measurement and Compensation
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Exact Decoding of Echo Disturbed Signals
Ports
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One 8-bit I/O-port with open drain output and optional
I
2
C Bus emulation support(Port0)
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Two 8-bit multifunction I/O-ports (Port1, Port3)
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One 4-bit port working as digital or analog inputs for the ADC (Port2)
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One 2-bit I/O port with secondary functions (P4.2, 4.3, 4.7)
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One 4-bit I/O-port with secondary function (P4.0, 4.1, 4.4) (Not available in P-SDIP 52)
