Bit Error Rate Tester | BERT 1005
Quantifi Photonics Ltd.
Version
2.04
42
Each time the data rate is changed, the clock synthesizer is unlocked for the frequency to change, and
then locked once the frequency is set. The lock status is indicated by the SYNTHESIZER VCO LOCK
indicator on the CLOCK tab.
After changing the frequency, the lock indicator turns to dark green ( ), and once the synthesizer is
locked to the new frequency it turns to light green ( ).
8.1.2
Configure the trigger out signal
To set the trigger-out frequency for the internal clock synthesizer, set the TRIGGER-OUT DIVIDE RATIO
according to the following steps:
1.
Click the CLOCK tab at the lower-left part of the page.
2.
Select an appropriate value from the TRIGGER OUT BAUD RATE DIVIDE RATIO drop-down list.
The frequency value in the TRIGGER OUT field will change accordingly.
3.
To set the trigger RF output power, select an appropriate value in the TRIGGER RF OUTPUT
POWER drop-down list.
Multiple BERT PXIe modules residing in the same PXIe chassis are automatically synchronized
using the internal PXIe chassis 10MHz clock.
