can identify a DS-200/300 board by recognizing the pattern read back
from the ID bits (seeFigure 10).
rate register bit 0
RR0
0
rate register bit 1
RR1
1
not used
OR2
2
not used
OR3
3
not used
OR4
4
not used
OR5
5
ID register bit 0
ID0
6
ID register bit 1
ID1
7
DESCRIPTION
NAME
BIT
Figure 9--- Options Register bit definitions
0
1
1
1
1
0
0
1
1
0
1
0
0
0
0
0
ID0
ID1
ID0
ID1
READ
WRITE
Figure 10 --- ID bit write/read table
The rate register allows software applications to check and set the data
rate multiplier. As long as the SW jumper is installed in jumper block J9,
the DS-200/300 gets the data rate multiplier from the value stored in the
rate register portion of the OR.
921.6 kbaud *
14.7456 MHz
x8
1
1
460.8 kbaud *
7.3728 MHz
x4
0
1
230.4 kbaud
3.6864 MHz
x2
1
0
115.2 kbaud
1.8432 MHz
x1
0
0
MAX DATA RATE
UART CLOCK SPEED
DATA RATE
MULTIPLIER
RR0
RR1
* - with 16750 UART only
Figure 11 --- Rate Register bit definition
A read of this register will return the value for the data rate multiplier that
the board is actually operating at, regardless of what is written to the
register. In other words, even when the data rate multiplier is being
controlled by the hardware jumper setting, the value read from this
register will correspond to that hardware jumper setting. This allows
applications software to detect the actual rate at which the board is
running.
5-2
Quatech Inc.
Summary of Contents for DS-200
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