Quatech MPAP-100, User Manual

Page 1: ... SYNCHRONOUS ADAPTER for PCMCIA Card Standard compatible machines User s Manual QUATECH INC TEL 330 655 9000 5675 Hudson Industrial Parkway FAX 330 655 9010 Hudson Ohio 44236 www quatech com Quatech MPAP 100 User s Manual 1 ...

Page 2: ...e voids all warranty rights Although every attempt has been made to guarantee the accuracy of this manual Quatech Inc assumes no liability for damages resulting from errors in this document Quatech Inc reserves the right to edit or append to this document at any time without notice Please complete the following information and retain for your records Have this information available when requesting...

Page 3: ...t to which it refers at any time and without notice The authors have taken due care in the preparation of this document and every attempt has been made to ensure its accuracy and completeness In no event willQuatech Inc be liable for damages of any kind incidental or consequential in regard to or arising out of the performance or form of the materials presented in this document or any software pro...

Page 4: ...oring The Status Of PCMCIA Cards 25 5 3 OS 2 Client Driver Configuration Examples 24 5 2 3 Hot Swapping 24 5 2 2 Auto Fallback configuration 24 5 2 1 Tying a configuration to a particular socket 23 5 2 OS 2 Client Driver Installation 23 5 1 System Requirements 23 5 OS 2 Software Installation 22 4 3 Configuration Options 18 4 Windows 95 98 Installation 17 3 4 DOS Enabler Examples 16 3 3 4 Releasing...

Page 5: ...pin 22 56 19 1 SYNCA pin 10 55 19 External Connections 54 18 Receive FIFO Timeout Register 53 17 Receive Pattern Count Register 52 16 Receive Pattern Character Register 51 15 FIFO Control Register 50 14 FIFO Status Register 49 13 Interrupt Status Register 47 12 Configuration Register 45 11 Communications Register 44 10 7 Receive FIFO timeout 42 10 6 Receive pattern detection 42 10 5 Accessing the ...

Page 6: ...ocols such as IBM Bisync and bit oriented synchronous protocols such as HDLC and SDLC The SCC also offers internal functions such as on chip baud rate generators and digital phase lock loop DPLL for recovering data clocking from received data streams Because the PCMCIA 2 1 standard does not include a direct memory access DMA interface the MPAP 100 supports only interrupt driven communications To c...

Page 7: ...er DOS it is also possible to use the Quatech MPAP 100 Enabler program Software installation and configuration is covered in other chapters of this manual 3 Attach the narrow connector on the supplied cable to the socket on the end of the MPAP 100 The connector is keyed so that it can only be inserted in one orientation The connector should attach firmly and smoothly Do not force the connector int...

Page 8: ...re required no yes Automatic configuration of MPAP 100 upon insertion Hot Swapping socket controller Intel 82365 or compatible only PCMCIA card and Socket Services socket independent Interfaces to DOS executable DOS device driver File type MPAP1EN EXE MPAP1CL SYS File name Enabler Client Driver Table 1 Client driver versus enabler for DOS Windows 3 x IMPORTANT Do not use both the client driver and...

Page 9: ... and must be separated from other desired configurations by a space on the command line Within each desired configuration parameters are separated using commas no spaces In the descriptions below replace the symbols with the appropriate numeric values 1 Copy the file MPAP1CL SYS from the MPAP 100 distribution diskette onto the system s hard drive 2 Using an ASCII text editor open the system s CONF...

Page 10: ...S file 7 If the Client Driver reports the desired configuration the installation process is complete and the MPAP 100 may be removed from the system if desired 8 If configuration of the card fails the client driver will display an error message If Invalid command line option is displayed correct the entry in the CONFIG SYS file and reboot the computer again If Card and Socket Services not found is...

Page 11: ...is helpful if the user allows Card Services to select resources instead of specifying them on the command line ...

Page 12: ...C MPAP 100 MPAP1CL SYS s0 b300 i5 Example Attempt to configure an MPAP 100 inserted into any socket with a base address of 300 hex and IRQ 5 If address 300 hex or IRQ 5 is unavailable attempt to configure the card with a base address assigned by Card Services and IRQ 10 If IRQ 10 is also unavailable attempt to configure the card with a base address and an IRQ assigned by Card and Socket Services D...

Page 13: ...on of high DOS memory when configuring an MPAP 100 This region is 1000H bytes 4KB long and by default begins at address D0000H the default address may be changed using the W option If a memory manager such asEMM386 QEMM or 386Max is installed on the system this region of DOS memory must be excluded from the memory manager s control Consult the documentation provided with the memory manager softwar...

Page 14: ...ee digit hexadecimal value ending in 0 This parameter is always required when configuring a card I The interrupt level IRQ of the MPAP 100 This decimal number must be one of the following values 3 4 5 7 9 10 11 12 14 15 or 0 if no IRQ is desired This parameter is always required when configuring a card W optional The base address of the memory window used by the enabler This two digit hexadecimal ...

Page 15: ...do this MPAP1EN S R W S The PCMCIA socket into which the MPAP 100 will be inserted This value is a decimal number ranging from 0 to 15 This parameter is always required when releasing a card s configuration R Release the resources previously allocated to the MPAP 100 This parameter is always required when releasing a card s configuration This option must not be used when configuring an MPAP 100 W ...

Page 16: ...ple Configure the MPAP 100 in socket 1 with a base address of 300H and IRQ 3 using a configuration memory window at segment D800 MPAP1EN EXE s1 b300 i3 wd8 Example Release the configuration used by the MPAP 100 in socket 0 MPAP1EN EXE s0 r Example Release the configuration used by the MPAP 100 in socket 1 using a configuration memory window at segment CC00 MPAP1EN EXE s1 r wcc ...

Page 17: ... INF file to determine the system resources required by the MPAP 100 searches for available resources to fill the boards requirements and then updates the hardware registry with an entry that allocates these resources The Syncdrive DLL and VxD can then be used to access the card 4 1 Using the Add New Hardware Wizard The following instructions provide step by step instructions on installing the MPA...

Page 18: ...ce Click the Next button to continue 3 On the next dialog select the CD ROM drive checkbox Insert the Quatech COM CD shipped with the card into the CD ROM drive Click the Next button 4 Windows should locate the INF file on the CD and display a dialog that looks like this Click the Next button ...

Page 19: ...5 Windows will copy the INF file from the CD and display a final dialog indicating that the process is complete Click the Finish button ...

Page 20: ...lick the Device Manager tab located along the top of the System Properties box 3 Double click the device group Synchronous_Communication The MPAP 100 model name should appear in the list of adapters 4 Double click the MPAP 100 model name and a properties box should open for the hardware adapter 5 Click the Resources tab located along the top of the properties box to view the resources Windows has ...

Page 21: ...Options If the Use Automatic Settings box is unchecked various options can be enabled by selecting a different basic configuration in the Setting based on dropdown box Revision B5 hardware and later only 0000 Factory default Suggested for nearly all customers 0001 Drive SYNC input of SCC channel A with the Remote Loopback bit of Communications Register see page 39 Otherwise the SYNC input is undef...

Page 22: ...card The client driver will attempt to configure an MPAP 100 with the first available configuration listed from left to right on the command line Each desired configuration must be enclosed in parentheses and must be separated from other desired configurations by a space on the command line Within each desired configuration the parameters are separated using commas no spaces 1 Copy the MPAP100 SYS...

Page 23: ...ticular socket A configuration can be made specific to a socket by appending Sx after the closing parenthesis where X is the desired socket number 5 2 2 Auto Fallback configuration OS 2 Card Services is capable of automatically determining a configuration for a PCMCIA device but due to limitations in Quatech s Syncdrive driver software the client driver does not support this feature This support i...

Page 24: ...If an MPAP 100 is inserted into socket 2 configure it at base address 110 hex and IRQ 15 If any of these resources are not available the card will not be configured Up to two MPAP 100s can be used DEVICE C MPAP 100 MPAP100 SYS 300 5 S1 110 15 S2 5 4 Monitoring The Status Of PCMCIA Cards OS 2 Warp provides a utility called Plug and Play for PCMCIA that can be used to monitor the status of each PCMC...

Page 25: ...2 was installed add it by using the Selective Install facility in the System Setup folder Full PCMCIA support is built into OS 2 Warp 3 0 and later On OS 2 2 1 and 2 11 PCMCIA Card Services is built in but you must add Socket Services separately ...

Page 26: ...he MPAP 100 with the settings expected by the Syncdrive application before the application tries to use the card Under Windows 95 98 the card is automatically configured To find the settings click the right mouse button on the My Computer icon and select Properties Select the Device Manager tab and double click the card s entry under the Synchronous Communication section Select the Resources tab t...

Page 27: ...ss space is reserved for future use The MPAP 100 address map is shown in Table 2 Reserved Base F Reserved Base E Receive FIFO Timeout Register Base D Receive Pattern Count Register Base C Receive Pattern Character Register Base B FIFO Control Register Base A FIFO Status Register Base 9 Interrupt Status Register Base 8 Reserved Base 7 Reserved Base 6 Configuration Register Base 5 Communications Reg...

Page 28: ...he SCC bit is set do an SCC software interrupt acknowledge by reading Read Register 2 in channel B of the SCC The value read can also be used to vector to the appropriate part of the ISR 4 Service the SCC interrupt by reading the receiver buffer writing to the transmit buffer issuing commands to the SCC etc 5 Write a Reset Highest Interrupt Under Service IUS command to the SCC by writing 0x38 to W...

Page 29: ...generation and checking Automatic zero insertion and deletion Automatic flag insertion between messages Address field recognition I field residue handling CRC generation and detection SDLC loop mode with EOP recognition loop entry and exit Byte oriented Synchronous Communications Internal external character synchronization 1 or 2 sync characters in separate registers Automatic Cyclic Redundancy Ch...

Page 30: ...port The only exception to this rule is when accessing the transmit and receive data buffers These registers can be accessed with the two step process described or with a single read or write to the data port The following examples illustrate how to access the internal registers of the SCC Table 3 on page 26 describes the read registers and Table 4 on page 27 describes the write registers for each...

Page 31: ... RR0 and then reading or writing data to the SCC buffers via CPU port accesses Interrupts on the SCC can be sourced from the receiver the transmitter or External Status conditions At the event of an interrupt Status can be determined then data can be written to or read from the SCC via CPU port accesses Further information on this subject is found on page 23 For block transfer mode DMA transfers a...

Page 32: ...ol and reset WR9 Transmit buffer WR8 Special HDLC Enhancement Register WR7 Sync character 2nd byte or SDLC Flag WR7 Sync character 1st byte or SDLC address field WR6 Transmitter initialization and control WR5 Transmit Receive miscellaneous parameters and codes clock rate stop bits parity WR4 Receiver initialization and control WR3 Interrupt vector WR2 Interrupt control Wait DMA request control WR1...

Page 33: ...or 64 Baud_Rate desired baud rate for Clock_Frequency 9 8304 MHz 3FFE hex 16382 300 1FFE hex 8190 600 0FFE hex 4094 1200 07FE hex 2046 2400 03FE hex 1022 4800 01FE hex 510 9600 00FE hex 254 19200 007E hex 126 38400 Time Constant Baud Rate Table 5 time constants for common baud rates 9 3 SCC Data Encoding Methods The SCC provides four different data encoding methods selected by bits 6 and 5 in WR10...

Page 34: ...and RTxCA from the cable The W REQB signal is used to generate DMA requests between the SCC and the external FIFOs if channel B is used for receive 9 4 2 Extra clock support for channel A The TRxCB clock output can be routed back to RTxCA as another way to use the channel B baud rate generator to derive an independent clock for the channel A receiver This is controlled by the RCKEN bit in the Comm...

Page 35: ...ill work Write Control Port A set pointer bits for desired register Read or Write Control Port A read or write desired channel A register Write Control Port B set pointer bits for desired register Read or Write Control Port B read or write desired channel B register The following sequences will NOT work Write Control Port A set pointer bits for desired register Read or Write Control Port B read or...

Page 36: ...are enabled they are accessed through either the channel A or channel B SCC Data Port address Writing to Base 0 or Base 2 will cause a byte to be written into the transmit FIFO Reading from Base 0 or Base 2 will cause a byte to be read from the receive FIFO The FIFOs cannot be accessed if they are disabled If the FIFOs are disabled reads or writes of the SCC Data Ports access the receive or transm...

Page 37: ... various SCC registers need to be set in a specific manner as shown on the following pages Because the data transfer between the FIFOs and the SCC is controlled entirely by hardware per character transmit and receive interrupts should be disabled Interrupts on transmit underruns and or special receive conditions should usually be enabled so that end of frame conditions can be detected IMPORTANT Th...

Page 38: ...A for W REQA timing 1 4 Assert transmit DMA request when entry location of internal FIFO is empty 0 5 WR7A Enable WR7A 1 0 WR15A Enable DMA request on transmit on DTR REQA 1 2 WR14A Disable transmit interrupts 0 1 Enable receive interrupts on special conditions only recommended or disable them completely 11 or 00 4 3 Use W REQA for receive 1 5 Set W REQA for DMA Request mode 1 6 Enable DMA request...

Page 39: ...y recommended or disable them completely 11 or 00 4 3 Use W REQB for receive 1 5 Set W REQB for DMA Request mode 1 6 Enable DMA request on W REQB This bit should be set after the other bits in WR1 are set as desired 1 7 WR1B Assert transmit DMA request when entry location of internal FIFO is empty 0 5 WR7A Enable WR7A 1 0 WR15A Disable DMA request on transmit on DTR REQA 0 2 WR14A Disable transmit...

Page 40: ...SCC See Table 10 on page 41 for details Software can read data from the receive FIFO as desired RX_PAT bit 3 Special receive pattern detected Software can read bytes from the receive FIFO until the FIFO is empty Receive data timeout with non empty FIFO Software can read at least 512 bytes from the receive FIFO RX_FIFO bit 2 Receive FIFO filled past the half full mark Software can write at least 51...

Page 41: ... are enabled The SCC channel A and channel B control port registers are always accessible regardless of whether the external FIFOs are enabled or disabled While the FIFOs are enabled SCC data port accesses are redirected to the FIFOs Access to the SCC s transmit or receive registers while the FIFOs are enabled is possible indirectly by using the control port and register 8 Any writes of SCC Write ...

Page 42: ... text character to be received or for three consecutive pad characters to be received For byte synchronous operation with simple unique markers in the data stream this feature may be quite useful Even if it is not however the MPAP 100 can certainly be operated with per character interrupts enabled and the external FIFOs disabled The tradeoff will be a heavier interrupt burden and possibly somewhat...

Page 43: ...ved a receive FIFO interrupt is generated and RX_FIFO bit in the Interrupt Status Register see page43 is set A character time is approximated by counting eight ticks of the bit clock To use this feature the receive clock must be output on TRxCA It can come from either an external source or from the channel A baud rate generator While the RTxCA signal is typically used for a receive clock it is not...

Page 44: ...tor Bit 5 LLEN Local Loopback Enable When set logic 1 this bit allows the DTE to test the functioning of the DTE DCE interface and the transmit and receive sections of the local DCE The DCE device must support local loopback for this to work When cleared logic 0 no testing occurs LLEN can also be used as a software controlled general purpose output Bit 4 RLEN Remote Loopback Enable SW_SYNC Softwar...

Page 45: ...ector In either case RCLK is always transmitted on pin 11 of the DB 25 connector Bit 2 TCKEN Transmit Clock Source When set logic 1 this bit allows the transmit clock TCLK to be generated by the TRxC pin on channel A of the SCC When cleared logic 0 the DTE receives TCLK on pin 15 of the DB 25 connector In either case TCLK is always transmitted on pin 24 of the DB 25 connector Bits 1 0 Reserved alw...

Page 46: ...FOs including MPAP 100 Revision A cards will return 0 in this bit location Bit 6 Reserved always 0 Bits 5 4 INTS1 INTS0 Interrupt Source and Enable Bits These two bits determine the source of the interrupt The two sources are interrupt from the SCC INTSCC and interrupt on Test Mode INTTM Only one interrupt source can be active at a time Below is the mapping for these bits Note that FIFO related in...

Page 47: ...xternal FIFOs when enabled The transmit data FIFO is always used with SCC channel A The receive data FIFO may be used with SCC channel A by setting RXSRC to logic 0 or with SCC channel B by setting RXSRC to logic 1 See page 29 for information on using channel B W REQA DTR REQA Transmit DMA W REQB W REQA Receive DMA RXSRC 1 RXSRC 0 Bit 0 Reserved always 0 ...

Page 48: ...imes in the received data stream where n is the value set in the Receive Pattern Count Register This bit is set logic 1 to indicate the interrupt It remains set until cleared by writing a 1 to this bit Bit 2 RX_FIFO Receive FIFO Interrupt The receive FIFO interrupt occurs when the number of bytes held in the external receive FIFO rises above the half full mark or when a receive FIFOtimeout occurs ...

Page 49: ... receive FIFO is completely full The FIFO will accept no more data from the SCC Bit 5 RXH Receive FIFO Half Full This bit is set logic 1 while the external receive FIFO is at least half full Bit 4 RXE Receive FIFO Empty This bit is set logic 1 when the external receive FIFO is completely empty Bit 3 Reserved always 0 Bit 2 TXF Transmit FIFO Full This bit is set logic 1 when the external transmit F...

Page 50: ...pattern detection circuitry Clear this bit logic 0 to disable pattern detection See page 37 for details on the receive pattern detection feature Bit 5 EN_TO Enable Receive Timeout Set this bit logic 1 to enable the external receive FIFO timeout Clear this bit logic 0 to disable the receive FIFO timeout See page 38 for details on the receive FIFO timeout feature Bit 4 RX_RESET Reset Receive FIFO Se...

Page 51: ...er is Base B hex This register can be ignored if the external FIFOs are not being used character value 0 255 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Table 14 Receive Pattern Character Register Read Write Bits 7 0 Receive Pattern Character This is the numeric value of the character to be detected See page 37 for details on the receive character pattern detection feature ...

Page 52: ...eing used counter value 0 255 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Table 15 Receive Pattern Count Register Read Write Bits 7 0 Receive Pattern Count This value is the number of times that the character stored in the Receive Pattern Character Register see page 46 must be consecutively detected for the receive character pattern detect interrupt to be generated See page 37 for details on t...

Page 53: ...16 Receive FIFO Timeout Register Read Write Bit 7 X16_MODE Clock Mode If this bit is set logic 1 the data clock is divided by 16 prescaled before it is fed to the timeout circuitry This is useful for asynchronous operation If this bit is clear logic 0 the data clock is not prescaled Bit 6 Reserved always 0 Bits 5 0 Timeout Interval This is the number of character times that must elapse before a no...

Page 54: ... B The SCC has no actual DSR inputs The DTE can transmit its transmit clock TCLK from the TRxCA pin of the SCC or receive TCLK on the same pin The DTE can also receive its receive clock RCLK on the RTxC pins on channels A B of the SCC or can generate RCLK using the TRxCB pin TCLK and RCLK can also be internally sourced from the channel A baud rate generator Figure 1 shows the DTE clock configurati...

Page 55: ...e SYNCA signal from the connector is used to drive the active low SYNC input of SCC channel A The signal is inverted by the RS 232 receiver so a positive voltage on pin 10 will assert SYNCA The SCC must be specifically programmed to recognize external synchronization 19 2 RING pin 22 If Card and Socket Services has set the SIGCHG bit in the PCMCIA Configuration Status Register to a logic 1 the RIN...

Page 56: ...X 17 N C 16 TRxCA pin DB TXCLK DCE X 15 N C 14 N C 13 N C 12 RTxCA or TRxCB pin RXCLK DTE X 11 SYNCA pin SYNCA X 10 N C 9 DCDA pin CF CD X 8 AB DGND 7 DCDB pin CC DSR X 6 CTSA pin CB CTS X 5 RTSA pin CA RTS X 4 RxDA pin BB RXD X 3 TxDA pin BA TXD X 2 CGND 1 Table 17 Connector Pin Definitions 19 3 Null modem cables The MPAP 100 does not use a standard asynchronous PC serial port connector pinout Ty...

Page 57: ...D DATA CONNECTOR NOTATION RXD DIRECTION From DCE This signal transfers the data generated by the DCE in response to data channel line signals received from a remote DTE data station to the DTE CIRCUIT CA REQUEST TO SEND CONNECTOR NOTATION RTS DIRECTION To DCE This signal controls the data channel transmit function of the local DCE and on a half duplex channel the direction of the data transmission...

Page 58: ...TOR CONNECTOR NOTATION RING DIRECTION From DCE This signal indicates that a ringing signal is being received on the communication channel CIRCUIT CF RECEIVED LINE SIGNAL DETECT CARRIER DETECT CONNECTOR NOTATION CD DIRECTION From DCE This signal indicates to the DTE whether the DCE is conditioned to receive data from the communication channel but does not indicate the relative quality of the data s...

Page 59: ... for its received data CIRCUIT LL LOCAL LOOPBACK CONNECTOR NOTATION LLBK DIRECTION To DCE This signal provides a means whereby a DTE may check the functioning of the DTE DCE interface and the transmit and receive sections of the local DCE CIRCUIT RL REMOTE LOOPBACK CONNECTOR NOTATION RLBK DIRECTION To DCE This signal provides a means whereby a DTE or a facility test center may check the transmissi...

Page 60: ...ale D 25 connector Transmit drivers RS 232 compatible 600 kbps typical maximum data rate Receive buffers RS 232 compatible 600 kbps typical maximum data rate I O Address range Sixteen byte contiguous range required determined by PCMCIA system Interrupt levels One IRQ required determined by PCMCIA system DMA channels Not supported by PCMCIA 2 1 bus Power requirements 115 mA at 5 volts typical ...

Page 61: ...function of the Card and Socket Services software is to track which system resources memory addresses I O addresses IRQs etc are available for assignment to inserted PCMCIA cards Occasionally Card Services may incorrectly determine that a particular resource is free when it is actually in use or vice versa Most DOS based Card and Socket Services generate a resource table in a file typically in the...

Page 62: ...the system this region of DOS memory must be excluded from the memory manager s control Consult the documentation provided with the memory manager software for instructions on how to exclude this memory region Some systems use the high memory area for BIOS shadowing to improve overall system performance In order for the enabler to operate BIOS shadowing must be disabled in the address range specif...

Page 63: ...e base address or IRQ value may be out of range Make sure that the base address is a hexadecimal number between 100 hex and 3F0 hex ending in 0 Make sure that the IRQ is a decimal number between 2 and 15 ...

Page 64: ...MPAP 100 User s Manual Revision 2 22 March 2004 P N 940 0090 222 Quatech MPAP 100 User s Manual i ...