LPWA Module Series
BG95&BG96 Compatible Design
BG95&BG96_Compatible_Design 13 / 47
3
Pin Definition
3.1. Pin Assignment
The following figure shows the pin assignment of BG96 and BG95.
R
E
S
E
R
V
E
D
1
2
3
4
5
6
7
11
12
13
14
15
16
17
18
50
51
52
53
54
55
58
59
60
61
62
31
30
29
28
27
26
23
22
21
20
19
10
9
8
49
48
47
46
45
44
43
40
41
42
39
38
37
36
35
34
33
32
24
25
57
56
63
64
65
66
67
68
83
84
85
86
87
88
98
97
96
95
94
93
78
77
76
75
74
73
91
92
89
90
71
72
69
70
80
79
82
81
100
99
102
101
PSM_IND
ADC1
RESERVED
R
E
S
E
R
V
E
D
G
P
IO
26
ANT_GNSS
A
N
T
_
M
A
IN
AP
_
RE
A
DY
S
T
A
T
U
S
N
E
T
L
IG
H
T
PCM_CLK
PCM_SYNC
PCM_IN
PCM_OUT
W_DISABLE#
GND
USB_VBUS
USB_DP
USB_DM
RESERVED
RESERVED
RESERVED
RESERVED
PWRKEY
1)
D
B
G
_
R
X
D
D
B
G
_
T
X
D
A
D
C
0
V
D
D
_
E
X
T
D
T
R
G
N
D
USIM_CLK
USIM_DATA
USIM_RST
USIM_VDD
RI
DCD
RTS
TXD
RXD
VBAT_BB
USIM_GND
GND
CTS
I2C_SCL
I2C_SDA
USIM_PRESENCE
VBAT_BB
G
N
D
G
N
D
G
N
D
R
E
S
E
R
V
E
D
V
B
A
T
_
RF
V
B
A
T
_
RF
G
N
D
G
N
D
R
E
S
E
R
V
E
D
G
N
D
G
N
D
U
A
R
T
3
_
T
X
D
U
A
R
T
3
_
R
X
D
RESET_N
GPIO64
USB_BOOT
BG96
/
BG95
Top
View
PSM_IND
ADC1
3)
RESERVED
PCM_CLK
PCM_SYNC
PCM_DIN
PCM_DOUT
W_DISABLE#
GND
USB_VBUS
USB_DP
USB_DM
RESERVED
RESERVED
RESERVED
RESERVED
PWRKEY
1)
RESET_N
2)
G
P
IO
1
G
P
IO
2
AP
_
R
E
A
D
Y
S
T
A
T
U
S
N
E
T
_
S
T
A
T
U
S
D
B
G
_
R
X
D
D
B
G
_
T
X
D
A
D
C
0
V
D
D
_
E
X
T
M
A
IN
_
D
T
R
G
N
D
G
N
S
S
_
T
X
D
4
)
G
N
S
S
_
R
X
D
ANT_GNSS
USIM_CLK
USIM_DATA
USIM_RST
USIM_VDD
MAIN_RI
MAIN_DCD
MAIN_RTS
MAIN_TXD
MAIN_RXD
VBAT_BB
USIM_GND
GND
MAIN_CTS
I2C_SCL
I2C_SDA
USIM_DET
VBAT_BB
R
E
S
E
R
V
E
D
A
N
T
_
M
A
IN
G
N
D
G
ND
G
ND
R
E
S
E
R
V
E
D
V
B
A
T
_
RF
V
B
A
T
_
RF
G
ND
G
ND
RE
S
E
RV
E
D
G
ND
G
ND
GPIO3
USB_BOOT
GPIO4
GPIO5
GRFC1
GRFC2
GPIO6
GPIO7
GPIO8
GPIO9
PON_TRIG
Figure 1: BG96&BG95 Pin Assignment
