LTE Standard Module Series
EC20 R2.1 Mini PCIe Hardware Design
EC20_R2.1_Mini_PCIe_Hardware_Design 26 / 51
In auxiliary mode, the data is sampled on the falling edge of the PCM_CLK and transmitted on the rising
edge. The PCM_SYNC rising edge represents the MSB. In this mode, the PCM interface operates with a
256kHz, 512kHz, 1024kHz or 2048kHz PCM_CLK and an 8kHz, 50% duty cycle PCM_SYNC. The
following figure shows the timing relationship in auxiliary mode with 8kHz PCM_SYNC and 256kHz
PCM_CLK.
PCM_CLK
PCM_SYNC
PCM_DOUT
MSB
LSB
PCM_DIN
125us
MSB
1
2
32
31
LSB
Figure 9: Timing in Auxiliary Mode
Clock and mode can be configured by AT command, and the default configuration is master mode using
short frame synchronization format with 2048kHz PCM_CLK and 8kHz PCM_SYNC. In addition, EC20
R2.1
Mini PCIe’s firmware has integrated the configuration on some PCM codec’s application with I2C
interface. Please refer to
document [2]
for details about
AT+QDAI
command.
The following figure shows a reference design of PCM interface with an external codec IC.
PCM_DIN
PCM_DOUT
PCM_SYNC
PCM_CLK
I2C_SCL
I2C_SDA
Codec
Module
1.8V
2.
2K
2.
2K
BCLK
FS
DACIN
ADCOUT
SCLK
SDIN
B
IA
S
MIC_BIAS
MIC+
MIC-
SPKOUT-
Figure 10: Reference Circuit of PCM Application with Audio Codec