TITLE
PROJECT
Lorry XU
Woody WU
CHECKED BY
DRAWN BY
OF
A
6
5
4
3
2
1
SHEET
A
B
C
D
1
2
3
4
5
6
D
C
B
Quectel Wireless Solutions
SIZE
VER
14
11
1.0
DATE
2019/12/5
EG21-G
A2
Reference Design
To minimize crosstalk, the reset trace must be at least 20mil
R916 should be placed close to AR8033.
The traces of the resistor must be away from other
and the trace width needs to be at least 25mil.
EMI filter is reserved.
If LED pins are not used, please keep C0920/C0923/C0924=470pF.
SGMII_MDIO_DAT should be connected to the USIM2_VDD
MODE 2
MODE 1
MODE 0
MODE 3
Ethernet PHY Design
PHY_AD2
PHY_AD1
PHY_AD0
traces (especially the clock and MDI interface traces),
The two capacitors should be selected according to the actual
load capacitance of crystal and the board-level test results.
Close to AR8033
Notes:
1. In the following description, the SGMII data signal refers to the SGMII TX and RX differencial pair, and the SGMII control signal refers to the SGMII_MDIO_CLK, SGMII_MDIO_DATA, EPHY_RST_N and EPHY_INT_N.
3. Keep the maximum trace length of SGMII data signal less than 10 inches and keep the length difference between TX and RX signals less than 20mil.
4. The differential impedance of SGMII data signal is 100Ω±10%, and the reference ground of the area should be complete.
EXT_INT_SEL
5. Make sure the trace spacing between SGMII RX and TX signals is at least 3 times of the trace width, and is the same to the adjacent signal traces.
6. Module and AR8033 are recommended to be designed on the same PCB. The peripheral circuit layout of Ethernet PHY chip AR8033 should be designed on a
7. RJ45, network transformer, AR8033, and the SGMII interface should be placed as close as possible.
beside the module with a 1.5kΩ pull-up resistor.
away from other signal traces.
L0901, C0913 and C0914 need to be placed close to Pin 3.
2. SGMII data and control signals should be strictly surrounded with ground and kept away from RF, analog, clock and DC-DC signals etc.
four-layer PCB, and the second layer should be total grounded as the AR8033 reference GND.
1 MDC
2 RSTN
3 LX
4 VDD33
5 INT
6 XTLO
7 XTLI
8 AVDDL
9 RBIAS
10 VDDH_REG
11 TRXP0
12 TRXN0
13
AVDDL
14
TRXP1
15
TRXN1
16
AVDD3
3
17
TRXP2
18
TRXN2
19
AVDDL
20
TRXP3
21
TRXN3
22
NC
23
LED
_AC
T
24
LED
_1000
25
CLK_25M
26
LED_10_100
27
RXD3
28
RXD2
29
VDDIO_REG
30
RXD1
31
RXD0
32
RX_DV
33
RX_CLK
34
TX_EN
35
GTX_CLK
36
TXD0
37
TXD1
38
TXD2
39
TXD3
40
WO
L_INT
41
SD
42
SO
N
43
SO
P
44
AVDDL
45
SIN
46
SIP
47
DVDDL
48
MD
IO
49
GN
D
U901
AR8033-AL1B-R
R903
NM_100K
C910
NM_1μF
R916
2.37K 1%
R908
10K
R906
NM_10K
C921
0.1μF
C925
0.1μF
C
926
0.1μF
C911
10μF
C927
1μF
C928
0.1μF
FB902
BLM15AX700SN1D
C922
1μF
C916
0.1μF
C915
100pF
1
XTAL
2 GND
3
XTAL
4 GND
Y901
25MHz
C917
10pF
C918
10pF
C924
NM/470pF
C923
NM/470pF
C919
NM
C920
NM/470pF
D901
GREEN
R915
510R
R901
0R
C908
0.1μF
C909
0.1μF
R904
0R
R907
0R
+
C904
100μF
C902
33pF
C901
10pF
C903
100nF
C912
0.1μF
FB901
BLM15AX700SN1D
R905
NM_10K
L901
4.7μH
C913
10μF
C914
0.1μF
C905
0.1μF
R914
10K
R909
10K
R913
10K
R910
10K
R911
10K
R912
10K
R917
10K
R918
10K
R902
1.5K
C906
2.2μF
C907
0.1μF
[3]
EPHY_RST_N
[3] EPHY_INT_N
AVDD_1
V
1
[11]
VDD33_SGMII
[3]
SGMII_TX_M
[3]
SGMII_RX_P
[3]
SGMII_RX_M
[3]
SGMII_TX_P
[11] VDD33_SGMII
[11] VDDH_2V5
[12]
TRXP0
[12]
TRXN0
[12]
TRXP1
[12]
TRXN1
[12]
TRXP2
[12]
TRXN2
[12]
TRXP3
[12]
TRXN3
[12]
LED_ACT
[12]
LED_1000
[3] SGMII_MDIO_DATA
[3] SGMII_MDIO_CLK
[11] VDD33_SGMII
CLK_25M
[11] VDD33_SGMII
[5,13]
VDD3V3
[3,4,5,6,13,14]
VDD_EXT
[11]
VDDH_2
V
5
[11]
AVDD_1V1
[11]
DVDD_1V1
[11]
DVDD_1V1
[11] AVDD_1V1
[11]
VDDH_2V5
[3]
USI
M
2_
VDD
AVDD_1
V
1
[11]
AVDD_1V1
[11] AVDD_1V1
