LTE Standard Module Series
EG25-GL_Hardware_Design 55 / 96
The following figure shows the simplified block diagram for Ethernet application.
Module
AR8033
Ethernet
Transformer
RJ45
SGMII
Control and
Management
MDI
Figure 27: Simplified Block Diagram for Ethernet Application
The following figure shows a reference design of SGMII interface with PHY AR8033 application.
SGMII_INT_N
120
DI
Ethernet PHY interrupt
1.8 V power domain.
If unused, keep it open.
SGMII_MDIO
121
DIO
SGMII management data
1.8/2.85 V power domain.
Require external pull-up to
SGMII_MDIO_VDD, and the resistor
should be 1.5 kΩ.
If unused, keep it open.
SGMII_MDC
122
DO
SGMII management data
clock
1.8/2.85 V power domain.
If unused, keep it open.
SGMII_MDIO_
VDD
128
PO
SGMII_MDIO pull up
power supply
Configurable power source.
1.8/2.85 V power domain.
If unused, keep it open.
SGMII Data Signals
SGMII_TX_M
123
AO
SGMII transmit (-)
Connect with a 0.1
μF capacitor, which is
close to the PHY side.
If unused, keep it open.
SGMII_TX_P
124
AO
SGMII transmit (+)
SGMII_RX_P
125
AI
SGMII receive (+)
SGMII_RX_M 126
AI
SGMII receive (-)
