LTE Standard Module Series
EG25-GL_Hardware_Design 47 / 96
PCM_CLK
PCM_SYNC
PCM_DOUT
MSB
LSB
PCM_DIN
MSB
1
2
32
31
LSB
125
μ
s
Figure 23: Auxiliary Mode Timing
The following table shows the pin definition of PCM and I2C interfaces which can be applied on audio
codec design.
Table 14: Pin Definition of PCM and I2C Interfaces
Clock and mode can be configured by AT command, and the default configuration is master mode using
short frame synchronization format with 2048 kHz PCM_CLK and 8 kHz PCM_SYNC. See
document [2]
for more details about
AT+QDAI
.
The following figure shows a reference design of PCM and I2C interfaces with external codec IC.
Pin Name
Pin No.
I/O
Description
Comment
PCM_DIN
24
DI
PCM data input
1.8 V power domain.
If unused, keep it open.
PCM_DOUT 25
DO
PCM data output
PCM_SYNC 26
DIO
PCM data frame sync
1.8 V power domain.
In master mode, it is an output signal.
In slave mode, it is an input signal.
If unused, keep it open.
PCM_CLK
27
DIO
PCM clock
I2C_SCL
41
OD
I2C serial clock (for external
codec)
An external pull-up to 1.8 V is required.
If unused, keep it open.
I2C_SDA
42
OD
I2C serial data (for external
codec)
