Wi-Fi&BT Module Series
FC21 Hardware Design
FC21_Hardware_Design 27 / 52
3.6. Other Interfaces
3.6.1. DBG_TXD Interface
DBG_TXD interface can be used for log output.
Table 14: Pin Definition of DBG_TXD Interface
3.6.2. 32KHz_IN Interface
The 32KHz clock is used in low power mode such as IEEE power saving mode and sleep mode. It serves
as a timer to determine when to wake up FC21 module to receive beacons in various power saving
schemes, and to maintain basic logic operations in sleep mode.
Table 15: Pin Definition of 32KHz_IN Interface
32KHz_IN pin is reserved on FC21 module since the sleep function is still to be developed.
Pin Name
Pin No.
I/O
Description
Comment
DBG_TXD
4
OD
Used for software
debugging
1.8V power domain.
Require external pull-up to 1.8V.
If unused, keep this pin open.
Pin Name
Pin No.
I/O
Description
Comment
32KHz_IN
19
DI
Low power.
External 32.768kHz clock
input.
1.8V power domain.
If unused, keep this pin
open.
NOTE
批注
[RL11]:
休眠时钟,默认由
EC2x
和
EG2x-G
模块提供。中
文里的引脚描述章节是这样表
述的。要以哪个为准