Smart LTE Module Series
SC66 Hardware Design
SC66_Hardware_Design 36 / 139
CSI2_CLK_P
183
AI
MIPI clock signal of
depth camera (
+
)
CSI2_LN0_N
186
AI
MIPI lane 0 data signal
of depth camera (
-
)
85Ω differential
impedance.
CSI2_LN0_P
185
AI
MIPI lane 0 data signal
of depth camera (
+
)
CSI2_LN1_N
188
AI
MIPI lane 1 data signal
of depth camera (
-
)
85Ω differential
impedance.
CSI2_LN1_P
187
AI
MIPI lane 1 data signal
of depth camera (
+
)
CSI2_LN2_N
190
AI
MIPI lane 2 data signal
of depth camera (
-
)
85Ω differential
impedance.
Can be multiplexed
into differential data of
the fourth camera (-).
CSI2_LN2_P
189
AI
MIPI lane 2 data signal
of depth camera (
+
)
85Ω differential
impedance.
Can be multiplexed
into differential data of
the fourth camera (+).
CSI2_LN3_N
192
AI
MIPI lane 3 data signal
of depth camera (
-
)
85Ω differential
impedance.
Can be multiplexed
into differential clock of
the fourth camera (-).
CSI2_LN3_P
191
AI
MIPI lane 3 data signal
of depth camera (
+
)
85Ω differential
impedance.
Can be multiplexed
into differential clock of
the fourth camera (+).
CSI0_CLK_N
78
AI
MIPI clock signal of
front camera (
-
)
85Ω differential
impedance.
CSI0_CLK_P
77
AI
MIPI clock signal of
front camera (
+
)
CSI0_LN0_N
80
AI
MIPI lane 0 data signal
85Ω differential
