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10
Rabbit 2000 Microprocessor
2.2.5 Slave Port
The slave port is designed to allow the Rabbit to be a slave to another processor, which
could be another Rabbit. The port is shared with parallel port A and is a bidirectional data
port. The master can read any of three registers selected via two select lines that form the
register address and a read strobe that causes the register contents to be output by the port.
These same registers can be written as I/O registers by the Rabbit slave. Three additional
registers transmit data in the opposite direction. They are written by the master by means
of the two select lines and a write strobe.
Figure 2-2 shows the data paths in the slave port.
Figure 2-2. Slave-Port Data Paths
The slave Rabbit can read the same registers as I/O registers. When incoming data bits are
written into one of the registers, status bits indicate which registers have been written, and
an optional interrupt can be programmed to take place when the write occurs. When the
slave writes to one of the registers carrying data bits outward, an attention line is enabled
so that the master can detect the data change and be interrupted if desired. One line tells
the master that the slave has read all the incoming data. Another line tells the master that
new outgoing data bits are available and have not yet been read by the master. The slave
port can be used to direct the master to perform tasks using a variety of communication
protocols over the slave port.
2.2.6 Timers
The Rabbit has several timer systems. The periodic interrupt is driven by the 32.768 kHz
oscillator divided by 16, giving an interrupt every 488 µs if enabled. This is intended to be
used as a general-purpose clock interrupt. Timer A consists of five 8-bit countdown and
reload registers that can be cascaded up to two levels deep. Each countdown register can
be set to divide by any number between 1 and 256. The output of four of the timers is used
to provide baud clocks for the serial ports. Any of these registers can also cause interrupts
and clock the timer-synchronized parallel output ports. Timer B consists of a 10-bit
CPU
Master
Processor
Slave Interface Registers
Input Register
Output Registers
Control
Rabbit
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