![background image](http://html2.mh-extra.com/html/rabbit/2000/2000_user-manual_3110256218.webp)
212
Rabbit 2000 Microprocessor
The MMIDR register shown in Table B-9 is used to enable and configure separate I & D
space support in addition to the /CS1 enable option used to improve the access time of
battery-backable SRAM.
NOTE:
Bits [7:5] and [3:0] were always written with zero in the original Rabbit 2000 chip.
Table B-9. MMU Instruction/Data Register (MMIDR = 0x010)
MMU Instruction/Data Register
(MMIDR)
(Address = 0x10)
Bit(s)
Value
Description
7:6
00
These bits are ignored and always return zeros when read.
5
0
Enable A16 and A19 inversion independent of instruction/data.
1
Enable A16 and A19 inversion (controlled by bits 0-3) for data accesses only.
This enables the instruction/data split. This is separate I and D space.
4
0
Normal /CS1 operation.
1
Force /CS1 always active. This will not cause any conflicts as long as the
memory using /CS1 does not also share an Output Enable or Write Enable with
another memory.
3
0
Normal operation.
1
For a DATASEG access, invert A19 before MBxCR (bank select) decision.
2
0
Normal operation.
1
For a DATASEG access: invert A16
1
0
Normal operation.
1
For root access, invert A19 before MBxCR (bank select) decision.
0
0
Normal operation.
1
For root access, invert A16
Summary of Contents for 2000
Page 1: ...Rabbit 2000 Microprocessor User s Manual 019 0069 041018 M...
Page 12: ...6 Rabbit 2000 Microprocessor...
Page 46: ...40 Rabbit 2000 Microprocessor...
Page 54: ...48 Rabbit 2000 Microprocessor...
Page 76: ...70 Rabbit 2000 Microprocessor...
Page 96: ...90 Rabbit 2000 Microprocessor...
Page 142: ...136 Rabbit 2000 Microprocessor...
Page 154: ...148 Rabbit 2000 Microprocessor...
Page 170: ...164 Rabbit 2000 Microprocessor...
Page 174: ...168 Rabbit 2000 Microprocessor...
Page 180: ...174 Rabbit 2000 Microprocessor...
Page 202: ...196 Rabbit 2000 Microprocessor...
Page 206: ...200 Rabbit 2000 Microprocessor...
Page 226: ......
Page 230: ...224 Rabbit 2000 Microprocessor...