1269 User Manual
Using The Enhanced Monitoring System 4-37
(bit 3 of SRE AND bit 3 of STB)
OR
(bit 4 of SRE AND bit 4 of STB)
OR
(bit 5 of SRE AND bit 5 of STB)
OR
(bit 7 of SRE AND bit 7 of STB)
where:
SRE
is the value as set by the *SRE command
STB
is the value of the Status Byte which may
be read with *STB? query or by
performing a serial poll (VXI read STB
command).
Bit 6 of the Status Byte is also known as the “Master Status
Summary” bit. When this bit transitions from a 0 to a 1, a
VXI Request True interrupt is generated by the EMS.
When this bit transitions from a 1 to a 0, a VXI Request
False interrupt is generated by the EMS.
The command has the format:
*SRE <SRE value>
where the “<SRE value>” is an integer numeric value in the
range 0 to 255. The value of bit 6 of this register is ignored,
since it does not make sense to “enable an interrupt when
an interrupt is generated”.
*SRE? Query
This query reads the value presently programmed for the
“Service Request Enable Register”. This reads the value
as programmed by the “*SRE” command.
*STB? Query
This query reads the value of the “Status Byte”. Each bit of
this register indicates a true/false status condition. When
the bit is set, the condition is TRUE; when the bit is cleared,
the condition is FALSE. The bit assignments are defined
by the IEEE-488.2 specification. The bit assignments are
as follows:
Bit 0 -
Not used. Always returns 0.
Bit 1 -
Not used. Always returns 0.
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