Specifications A-2
FSK Modulation
Operation
Current segment is sampled continuously. External low level
(below trigger level) programs carrier sample clock, external
high level (above trigger level) programs shifted frequency.
Sample clock changes coherently between frequencies.
Carrier Sample Clock Range
100mHz to 300MHz
FSK Source
External
Front panel BNC. Low level = carrier sample clock; High level
= hop frequency
Frequency Range
From 10MHz to DC
VXIbus Frequency Range
From 10MHz to DC
Ratio Between Carrier
and Hop Frequencies
1 through 65536
FSK Delay
Minimum 1 waveform cycle
Operating Modes
Normal
Continuous waveform is generated.
Triggered
Each input cycle generates a single output cycle.
Internal Trigger
An internal timer repeatedly generates a single output cycle.
Gated
External signal enables generator. First output cycle is
synchronous with the active slope of the triggering signal. Last
cycle of output waveform is always completed.
External Burst
Preset number of up to 1M cycles stimulated by an internal,
external, or manual trigger. This mode is available in FIXed
and USER modes only.
Internal Burst
An internal timer repeatedly generates a burst of up to 1M
counted output cycles. This mode is available in FIXed and
USER modes only.
Delayed Trigger
1 to 8 M clock cycles
Resolution
1 sample clock period
Accuracy
2 sample clock p system delay
Jitter
1 sample clock
Trigger Sources
Internal
Internal programmable rate generator
Period
From 20
µ
s to 1000 s
Accuracy
±
(1% + 0.5
µ
s)
External
Input
1) Front panel BNC
2) VXIbus (TTLTRG 0-3)
3) VXIbus ECLTRG0
Frequency
15 MHz to DC
Software
IEEE 488.2 *TRG, VXI Word Serial trigger command
System Delay
(trigger to waveform output)
Trigger Delay Mode Off
Standard/Arbitrary Waveforms
1 Sample Clock + 150 ns
Trigger Delay Mode On
Standard/Arbitrary Waveforms
2 Sample Clock + 150 ns
Summary of Contents for 3162A/B
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