Radio Shack Tandy 200, Technical Reference Manual

Page 1: ...Tandy 200 Technical Reference Manual 26 3861...

Page 2: ......

Page 3: ...ISHED BY RADIO SHACK INCLUDING BUT NOT LIMITED TO ANY INTERRUPTION OF SERVICE LOSS OF BUSINESS OR ANTICIPATORY PROFITS OR CONSEQUENTIAL OAMAGES RESULTING FROM THE USE OR OPERATION OF THE EQUIPMENT OR...

Page 4: ...s written permission from Tandy Corporation and or its licensor of any portion of this manual is prohibited While reasonable efforts have been taken in the preparation of this manual to assure its ac...

Page 5: ...erial Interface Circuit 2 20 LCD 2 30 Power Supply and Auto Power ON OFF Circuit 2 39 APPENDIX A INSTALLATIONS A 1 Installation of Operational RAMs and ROM A 1 Installation of Nickel Cadmium Batteries...

Page 6: ...eader Interface Circuit 2 15 21 Buzzer Control Circuit 2 15 22 RP5C01 Internal Block Diagram 2 16 23 Flowchart for the TIMER IC 2 18 24 Functional Block Diagram of the Serial Interface 2 21 25 RS 232C...

Page 7: ...nal Block Diagram C 1 C 12 Pin Configuration of 82C51A C 20 C 13 Function Setting Sequence C 24 C 14 Bit Configuration of Mode Instruction Asynchronous C 25 C 15 Bit Configuration of Mode Instruction...

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Page 9: ...1 Keyboard Can be used like the standard typewriter However the Tandy 200 does have a few special keys See Appendix B of this manual for more details 2 LCD Unit The Tandy 200 display has sixteen line...

Page 10: ...Figure 1 Front View...

Page 11: ...or transmit serial information When communicating directly with another Radio Shack computer a Null MODEM Adapter 26 1496 is required An 8 Cable Extender 26 T497 may also be required SYSTEM BUS Connec...

Page 12: ...200 capabilities 3 Battery compartment When not connected to an AC power source the Tandy 200 gets its power from four AA size batteries that must be installed in this compartment If the Tandy 200 ha...

Page 13: ...Amp for Power Supply Figure 5 LCD PCB Standard RAMs 8 K byte x 3 xtal for Timer IC Timer IC Reserved through Holes for Modification Jumper Module IC Sockets for IC Socket for Optional ROM Memory Powe...

Page 14: ...ies Batteries Four type AA Alkaline manganese batteries Operation time 7 days at two hours day Note Without I O units at normal temperature Memory protection battery on Main PCB Battery Rechargeable b...

Page 15: ...ions Audio cassette interface Data Rate Printer interface Conforms to Centronics interface standards Handshake Signal TXR Transmit Data RXR Receive Data RTS Request to Send CTS Ciear to Send DSR Data...

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Page 17: ...section describes the theory of operation for the Tandy 200 Figure 7 shows how this section is organized and highlights significant areas I CO CJJ III ji til lis id 11 6 u 5_ HI So li r h Q J b I si...

Page 18: ...face 82C51AUSART This is the Universal Synchronous Asynchronous Receiver Transmitter which controls the serial interface such as the RS 232C and MODEM SLA5080FOU Gate Array This LSI consists of the la...

Page 19: ...J D DON TROLL Eft E 8 m 3 en 2 3...

Page 20: ...in the SLA5080FOU is shown in Figure 9 AL E TNTA o H x D Q H h Figure 9 Functional Block Diagram of Bus Separation Circuit Memory The Tandy 200 uses a 32K byte ROM for the MSPLAN 40K byte ROM for BAS...

Page 21: ...QQDD RDM 9 NK JOKE 3EK 9 W J J FFF ADPP DFFF EGDQ 8HS_ RAM 8KB 24K_B 8KB 8KB JKB SAW AANK 5 JKB JK _ _2jlK_B _3KB STANDARD Figure 10 Memory Map 2 5...

Page 22: ...i go 04 1 HC _L end vcc 29 m T AD Al A2 4 Al i A2 4 A3 S A4 Ab AS AT AB A9 A 10 An A12 4 A5 J AG 35 A7 Ijwr AID aii Nt nn N9 r nc S I mc a c Q2A 028 0 X Figure 11 Internal Wiring diagram of RAM packag...

Page 23: ...uit in the SLA5080FOU The latch AA0036 stores the bank selection data sent from the CPU with the Y5 and WR signal The decoder AA0038 is enabled by the memory address 0O00H to 9FFFH for ROMs and the de...

Page 24: ...24 with the IO M signal At the latch AA0063 the chip enable terminals G1 and G2 are connected to the ALE signal passing through the inverter because the AD0 AD7 signals are the multiplexed bus The I O...

Page 25: ...a T 7 1 H o a o a o O u 0 a a K t z z Ul t ut a r H o o X t z 8 w t a o Ul w z o u X _JI in ui z t S o o o J JO 5 Q o 3 in z o H CO D z Ctun UJ i_ 5 CO IS V Ul si a _l U o t oo U O U O U O u o U O U O...

Page 26: ...CD CD ti B Q s 1 1 1 Q 2 O O CD CD a CD CD CD CD CD CD 3 CZ Q CZ O O ti o m m 0 4 1 cr m to r CO CO CO 0 to j j j i CO eg X CO 3 a 3 CI LU g co Zl CL CL O o c c ZJ a c t3 Q co m CO CO CO CO 0 CO to r...

Page 27: ...the CPU The STB K signal is generated in the SLA5080F0U when the CPU assigns EO EFH to the I O port address The CPU starts the key scan operation when the RST 7 5 interruption is accepted This interr...

Page 28: ...cassette recorder AUX jack Figure 16 shows the write circuit of the cassette interface oo I SI OD PUI rLTLTLn Figure 16 Write Circuit of Cassette Interface Read Circuit The signal input from the earp...

Page 29: ...8 bit parallel data PA0 PA7 from 81C55 is sent to the printer Then by writing in data 1 into bit 1 of the output port specified by I O address EO EFH the PSTB signal is generated in the SLA5080FOU an...

Page 30: ...of the CPU When the bar code reader reads the first white part of the bar code a L level signal is generated then inverted by M1 As soon as RST 5 5 interruption occurs the CPU starts the data input op...

Page 31: ...to sound the buzzer with the specified frequency by emitting a signal from the PB5 terminal of the 8iC55 and the other by using timer output TO and the BUZZER signal P82 of the 81C55 In addition the B...

Page 32: ...he PBS is L How long the sound is heard depends on the second parameter of SOUND command in BASIC Clock Control Circuit A TIMER IC RP5C01 on the memory PCB is used in the clock control circuit so that...

Page 33: ...T _J o o LU o o s o o TestO Alarm Reset a X i Testi Timer Reset C J o X XX z UJ E IN O V X 1 ic CO a X X XX X X Z UJ Si E i 2 o a t en a One sec Counter Ten sec Counter One min Counter Ten min Counte...

Page 34: ...REGISTER TO fla L A3 2 A A d3 02 onto ftOrfft js_ 1 Q 1 Q X i 1 o ftfSFT THF TlUFfl _3_M aJ ArJ 01I02 dsIdo S WRITE THE CUfiflEMT TIME anG OaT 1 1 AZAI AD jo o jo f a 2 AL AC D3Jcjjpj VALUE U H ACH 3T...

Page 35: ...TO Dl ff SFT TrtE ALApu PEG1 TER Id 3 L Hfj u WRITE THF ALARM TTME Mti DA 1 E A AH D3jDg pi Dq qj VALUE QF EACH ITEk kJAJA AtJ ENABLE T HE A AfiM QljTRljT l klU C f FNn J READ THE ALARW TJME ANQ DATE...

Page 36: ...iagram of the serial interface circuit In this figure the TO signal basic timing clock for the USART defines the transmission reception baud rate To transmit and receive the serial data from externa d...

Page 37: ...j i 2 i S 3 pS f i 9 I J V7 2 IAW SI r i i a o z i f o Q D 4 1 U LI Vft t WMs r 1 Vh t L i _ g w o 1 y O 3 i I 5 8 1 n E IL 5 3 u o ini 5 s 1 3 a o V n o O J 2 J r iu a o j D S o u Q o a 3d Figure 24...

Page 38: ...s not used To make this condition pin 14 of M23 is connected to the ground During the MODEM mode the RTS signal is used as the self loopback signal and it is sent back to the CTS terminal The DSR sign...

Page 39: ...y the inverters connected in parallel and then are output as RS 232C transmission signals In the RS 232C reception circuit the DSRR CTSR and RXR signals from the external RS 232C line are subjected to...

Page 40: ...S s k I i I L A MW W in tt S Kf fe Kf fc V CO o Cl CVJ VJ a to w _ M 1 c m Q O 1 C I O CO fO CM N 5 2 s s Figure 26 RS 232C Interface Circuit 2 24...

Page 41: ...ut to MODE input terminal and it switches between the originate mode or the answer mode This signal is output from the PB1 terminal of the 81C55 R7I I5M VDO TO TRANSMISSION FILTER CIRCUIT uuinr FROM R...

Page 42: ...nal of MC14412 Also to check a carrier signal this signal is input to the demultiplexer M23 as the CDD signal in the RS 232C interface circuit Intermediate frequencies of the 3 stage active filter are...

Page 43: ...ed to the secondary side of the driver transformer The primary side of this transformer is connected to the telephone line via the connector TXMD RXMD The ACP DIR switch is used in the MODEM mode rela...

Page 44: ...D li fe o J CD O Figure 30 MODEM Connector Interface Circuit 2 28...

Page 45: ...SC TCM5089 The enable TNE signal input to this IC is created by NANDing the DTR signal and RS232C signal That is when the DTR signal becomes H during MODEM mode this IC will be in the enable state Th...

Page 46: ...LCD Control Circuit of the Tandy 200 consists of the LCDC HD61830B and 8K byte RAM The LCDC generates driving signals for LCD by receiving the instructions and data from the CPU The driving signals fo...

Page 47: ...5z z 3x3 idI inn Z 3 wo u uia a _ o 1 CO j ilLs a u n l a A o a Q iS ij o s o h 01 o M 3 ft o ft o O S u u u o J CD L a r Z u o g s 1 O UJ 3 Q O CD _ o 1 r t o 0 1 1 1 Z o J CK a m at 2jS a o a Z r I...

Page 48: ...the periodic frequency of one screen display and determines 80 Hz for the Tandy 200 The MB signal is used for changing the driver signal to AC because the continuous application of DC to the LCD would...

Page 49: ...Figure 33 Internal Block Diagram of HD61103 2 33...

Page 50: ...Figure 34 Output Waveform of HD61103 2 34...

Page 51: ...a are output The CL2 signal is used for the shift clock of the display data The MB signal changes output signals to AC The D1 signal is the data to display on the upper half of the LCD screen and the...

Page 52: ...n n Figure 36 Output Waveform of HD61100 2 36...

Page 53: ...he maximum voltage applied to the common electrode and segment electrode is the potential difference between V1 and V2 In addition a is the bias coefficient which determines from the standpoint of con...

Page 54: ...VI V2 1J VE V5 COMMON LINE V3 V3 V V NON ILLUMINATION SEGMENT LINE ILLUMINATION SEGMENT LINE Figure 37 Driving Waveform of LCD 2 39...

Page 55: ...sed for the input voltage to the DC DC converter circuit When the internal circuit is modified for use of Nickel Cadmium batteries VIN is supplied to the four Nickel Cadmium batteries installed into t...

Page 56: ...Figure 38 Power Distribution 2 40...

Page 57: ...at the base coil Then when the base potential progresses to a half cycle of the oscillation voltage it is biased in the forward direction T20 and T21 are switched ON once again In this way AC voltage...

Page 58: ...Figure 39 DC DC Converter and Low Power Detection Circuit 2 42...

Page 59: ...same time the LPS signal becomes H and is sent to the TRAP terminal of the CPU after inverted at M35 g When VDD reaches a constant DC level to operate the CPU T28 is switched on and T29 is switched o...

Page 60: ...signal if the automatic Power Off limit reaches the value corresponding with the 1st parameter of the POWER command in BASIC The remaining sequence follows the Power Down using the POWER switch Reset...

Page 61: ...Figure 40 Power Control and Reset Circuit 2 45...

Page 62: ...CA J i i l a s n M x X ET LU CM E 10 CM to VJ L _ t V o O o o C J W CM 1 i Figure 41 Power Up Down Sequence 2 46...

Page 63: ...2 Insert the optional ROM into the IC socket marked M308 Installation of Nickel Cadmium Batteries Remove the memory PCB Refer to Section II Disassembly Instruction Install the modification jumpers in...

Page 64: ...Cadmium batteries into the battery compartment Drill the screw hole on the battery cover using the tapping screw and secure the battery cover and bottom case Stick the red iabel on the battery cover F...

Page 65: ...CHARACTER CODE TABLE Keyboard Layout f r I I a A HZ D r C T 1 j 1 r ESC 12 3 4 At J 5 s tg U 91 1 1 DEL 8KSP TAB W E R T Y U n l B B P ENTEER CTRL A s D G H J K H L B CAPS LOCK SHIFT Z X C v e n m f...

Page 66: ...ress Address Address and data and data and date and dala and data and data and data and data signal bit signal bit signal bit signal bit signal bit signal bit signal bit signal bit signal bitO signal...

Page 67: ...RS 232C Interface Pin No Symbol Description 1 GND 2 TXR Transmit Data 3 RXR Receive Data 4 RTS Request to send 5 CTS Clear to send 6 OSR Data set ready 7 GND 8 CD Carrier detect 9 NC 10 NC 11 NC ia NC...

Page 68: ...Data 4 GND 5 PD1 Bit 1 of Print Data 6 GND 7 PD2 Bit 2 of Print Data a GND 9 PD3 Bit 3 of Print Data 10 GND 11 PD4 Bit 4 of Print Data 12 GND 13 PD5 Bit 5 of Print Data 14 GND 15 PD6 Bit 6 of Print D...

Page 69: ...HS 25 23 21 19 17 15 13 11 9 7 5 3 1 26 24 22 20 18 16 14 12 10 8 6 4 2 HHBHHHHHHEBHH Figure B 4 Printer Connector Cassette Interface Figure B 5 Cassette Connector MODEM Interface Figure B 6 MODEM Con...

Page 70: ...de Reader Interface Ptn No Symbol Description 1 NC 2 R x DB Receive data from bar code reader 3 NC 4 NC 5 NC 6 NC 7 GND 8 NC 9 VDD 1 2 3 4 S O G O O O O O O 6 7 8 9 Figure B 7 Bar Code Reader Connecto...

Page 71: ...1 0010 jCTBt R 19 13 OOO 10011 S 20 14 0O01010O c T 21 15 00010101 c U 22 IB 0O01O110 V 23 17 00010111 W 24 IS 00011000 B Decimal Hn Binary Dilplayid CiiBricter Keyboard Character 26 19 00011001 Y 26...

Page 72: ...70 46 010O011O F F 71 47 010001 11 G G n 48 01001000 H H 73 49 01001001 I I 4A 01001010 Decimal Max Binary Display Character Keyboard Character 75 4B 01001011 K K 76 4C 010O110O L L 77 40 O1OO1101 M...

Page 73: ...9 77 01110111 w w 120 7B 01111000 X X 121 79 01111001 y y 122 7A O111101O z 123 7B 01111011 s 124 7C 01111100 1 1 Decimal Hai Binary Diiplayed Cheractar Keyboard Character 12b 70 01111101 126 7E 01111...

Page 74: ...1O1O10O0 10101001 10101010 1 B 171 AB 10101011 13 y 17 AC 10101 100 K p 173 AO 1010110 K 174 AE 10101110 Decimal Hen Binary Ditplayad Character KeybodrtJ Character 175 AF 1 01 01 1 1 n 176 BO 1011000...

Page 75: ...A 217 09 11011001 1 B K 21B DA 11011010 6 B L DB DC B B 221 DD 11011101 s M 222 D 11011110 fe B c 223 DF 11011111 B z 224 Ef t 1 1 00000 B z Decimal rtax Binary Displayed Character Kayboard Character...

Page 76: ...Binary Jtplav d K ytoirri Character Chwactw 250 FA 11 11010 B K 251 FB 1 1 1 1 or i r H 252 FC ntnoo A T 253 FD 1111101 a a 254 FF 1111110 k 255 FF mini m c B 12...

Page 77: ...d in silicon gate C MOS technology and compatible with 8085A It is designed with same processing speed and lower power consumption compared with 8085A thereby offering a high level of system integrati...

Page 78: ...o lTi e2 fit d LiZ a a z C3 o v 4 k Figure C 1 Functional Block Diagram C 2...

Page 79: ...ne cycle It then becomes the data bus during the second and third clock cycles ALE Output Address Latch Enable It occurs during the first clock state of a machine cycle and enables the address to get...

Page 80: ...PU has received the HOLD request and that it will relinquish the bus in the next dock cycle HLDA goes low after the Hold request is removed The CPU takes the bus one half clock cycle after HLDA goes l...

Page 81: ...Can be used as a system reset The signal is synchronized to the processor clock and lasts an integral number of clock periods Xi X2 Input Xi and X2 are connected to a crystal to drive the internal cl...

Page 82: ...O CO c tr a X X X C o K o C 5 0 t X X x X f O o CD t J O CO eg CD U S 05 f X3 5 o i C i CO in l_ Q e 0 in in in r CO 1 in t rr co w K rr tx r cn a a s o J f O 0 Q I C g 5 u o o u o sz r u c rn u X3 O...

Page 83: ...ition to these features 80C85A has three maskable vector interrupt pins and one nonmaskable TRAP interrupt Interrupt and Serial I O The 80C85A has 5 interrupt inputs INTR RST 5 5 RST 6 5 RST 7 5 and T...

Page 84: ...ue to noise or logic glitches Figure C 3 illustrates the TRAP interrupt request circuitry within the 80C85A Note that the servicing of any interrupt TRAP RST 7 5 RST 6 5 RST 5 5 INTR disables all futu...

Page 85: ...d by the status of the three status lines IO M Si So and the three control signals RD WR and INTA See Table C 2 The status line can be used as advanced controls for device selection for example since...

Page 86: ...ce o o o CO o o O 1 O to o o O 12 g o o o _ o O c c o 0 o o U D XJ O O o 5 0 D ec o E 0 2 0 o E CD 2 O a CD oc O o S o z DC l z o 0 TJ CD o c J o Bus idle Bl DAD ACK OF RST TRAP HALT Table C 2 80C85A...

Page 87: ...co i CO i X X X X X X X co CO is X X X X o o co to CO to CO X X X X X o X CD co CD C xz u a H 1 h H 1 H 4 1 1 CO w u 1 t X t a o X 1 o to T3 CD Q c o o c Q Q w 0 u o U E o J nj o c o V a co c M T3 l C...

Page 88: ...IS o uJ r U _l U p a i ls i i Figure C 4 80C85A Basic System Timing C 12...

Page 89: ...I O consists of two 8 bit ports and one 6 bit port both general purpose The MSM81C55RS GS also contains a 14 bit programmable counter timer which may be used for sequence wave generation or terminal...

Page 90: ...y RD Input If this pin in low data from either the memory or ports is read onto the ADo 7 lines depending on the state of the IO M line WR Input If this pin is low data on lines ADo 7 is written intoe...

Page 91: ...ta Bus X Com mand Status PC 6 bits I Z PA Timer MSB Timer LS8 Boits a bits Figure C 7 Internal Register of 81 C55 A6 i O Address Selecting Register AT AS A4 A3 A2 A1 AO X X X X X internal command stat...

Page 92: ...imer if it is running NOP if Hie timer is not running 10 STOP AFTER TC Stops the timer when li reaches TC NOP it Ihe timer is not running 11 START If the timer is not running loads the mode and the co...

Page 93: ...de I O address of the PA register xxxxxOOl I O address of the PB register xxxxxCMO 4 PC Register The PC register may be used as an input port output port or control register depending on the programme...

Page 94: ...the second period of four Note 2 if an internal counter of the 81C55 receives a reset signal count operation stops but the counter is not set to a specific initial value or output mode When restarting...

Page 95: ...CPU after conversion Thus the device is used for serial data communication 82C51A configures a fully static circuit using silicon gate CMOS technology Therefore it operates on an extremely low power s...

Page 96: ...t status The device waits for the writing of mode instruction The min reset width is six clock inputs during the operating status of CLK CLK Input CLK signal is used to generate an internal device tim...

Page 97: ...nd Note TXRDY of status word indicates that transmit data character is receivable regardless of CTS or command If CPU write a data character TXRDY will be reset by the leading edge or WR signal TXEMPT...

Page 98: ...at high level if sync characters are received and synchronized If status word is read the terminal will be reset In external synchronous mode this is an input terminal If High on this input forces 82C...

Page 99: ...tate X 1 1 Data bus 3 state 1 1 Status CPU 1 1 Control word CPU 1 Data CPU 1 Data CPU Table C 6 Operation between 82C51A and CPU It is necessary to execute a function setting sequence after resetting...

Page 100: ...t or externa reset That is the writing of control word after resetting will be recognized as mode instruction Items to be set by mode instruction are as follows Synchronous Asynchronous mode Character...

Page 101: ...ifl C 16 tK 16x Six Character length 1 1 1 1 5 bits a bits 7 bits 8 bits arity check 1 i j 1 1 1 Disable Odd parity Disable Even panty Stop bit length 1 t 1 1 f Inhibit 1 bit 1 S bits 2 bits Figure C...

Page 102: ...Configuration of Mode Instruction Synchronous 2 Command Command is used for setting the operation of 82C51A It is possible to write a command whenever necessary after writing mode instruction and syn...

Page 103: ...break character Normal operation t Reset error flag 0 rr IMorrfiaJ operation RTS 1 RTS 0 RT 1 1 Infernal reset Normal operation Nata Search mode for aynchronoirs characters jn synchronous mode 1 Hunt...

Page 104: ...asyn chronous mode Stop bu cannot be detected Figure C 17 Bit Configuration of Status Word Standby Status It is possible to put 82C51A in standby status for the complete static configuration of CMOS W...

Page 105: ...an electric shutter that controls the passage of light If voltage is applied the transmission of light is blocked otherwise light is allowed to pass so that letters and numbers can be displayed Figure...

Page 106: ...Light b Voltage is app e W Front Polarizer Front Glass Electrode Twisted 90 L j wfom J Rear Glass Electrode Rear Polarizer Reflector mm YON Light is passed Bright Light is interrupted Dark Figure C 19...

Page 107: ...BLOCK DIAGRAM ABSOLUTE MAXIMUM RATINGS Item Symbol Rating Unit Terminal Voltage Vl 0 5 to 7 0 V Power Dissipation Pr 1 0 W Operating Temperature Topr to 70 C l tn r iturc j 55 to 125 C Storage Temper...

Page 108: ...nput Output Capacitance Q o Vno 0V pF Note This parameter is sampled and not 100 tested AC CHARACTERISTICS Vcc 5V 10 Ta to 70 C AC TEST CONDITIONS Input Pulse Levels 0 8 to 2 4V Input Rise and Fall Ti...

Page 109: ...e Time wc 120 150 ns Chip Selection to End of Write cw 85 100 ns Address Setup Time AS ns Address Valid to End of Write aw 85 100 ns Write Pulse Width wp 70 90 ns Write Recovery Time CST WE WRI 5 10 n...

Page 110: ...ing high to the end of write 3 AS s measured from the address valid to the beginning of write 4 t wr is measured from the end of writejo thejiddress change t WRi applies in case a write ends at CSI or...

Page 111: ...IRC m VIL min 0 3V 20jiA max at ra 0 40 C RC Read Cycle Time LOW Vcc DATA RETENTION WAVEFORM 11 CS1 ControlM Data Retention Mode CSl fcc 0 2V 0V LOW Vcc DATA RETENTION WAVEFORM 2 CS2 Controlladl Data...

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Page 113: ...764 BLOCK DIAGRAM PIN ARRANGEMENT ABSOLUTE MAXIMUM RATINGS Item Symbol Rating Unit Terminal Voltage VT 0 5 to 7 0 V Power Dissipation Ft 1 0 W Operating Temperature 7opr to 70 C Storage Temperature T...

Page 114: ...from the address valid to the beginning of write 4 twR s measured from the end of write to the address change ty m applies in case a write ends at CS1 or WE going high twR2 applies in case a write en...

Page 115: ...pF Note This parameter is sampled and not 100 tested AC CHARACTERISTICS Vcc 5V 10 Ta to 70 CI AC TEST CONDITIONS Input Pulse Levels 0 8 to 2 4V Input Rise and Fall Times 10ns Input and Output Timing R...

Page 116: ...Chip Selection to End of Write lew 80 85 100 ns Address Setup Time IAS ns Address Valid to End of Write IAW 80 85 100 ns Write Pulse Width twp 60 70 90 ns Write Recovery Time CS1 WE IWR1 5 5 10 ns CS...

Page 117: ...CS2 going high to the end of write 3 t AS is measured from the address valid to the beginning of write 4 twR is measured from the end of writejo the address change l WRl applies in case a write ends...

Page 118: ...lR rc ns VIL min 0 3V 20 A max at ra 0 40 C RC Rea Cycle Time LOW Vcc DATA RETENTION WAVEFORM 1 CS1 Controlled Data Retention Mode CS12CCC 0 2V LOW Vcc DATA RETENTION WAVEFORM 2 CS2 Controlled Data Re...

Page 119: ...e Vcc V Vcc 5 0 V Ambient Temperature Ta C SUPPLY CURRENT vi FREQUENCY ACCESS TIME vi LOAD CAPACITANCE 200ni 150n I20n lOOn Ta 25 C VCC M1N Frequency MHz Load Capacitance C pF ACCESS TIME v SUPPLY VOL...

Page 120: ...tafe Vcc V Supply Voltage Vcc V OUTPUT CURRENT vs OUTPUT VOLTAGE OUTPUT CURRENT vs OUTPUT VOLTAGE Vce 5V Output High Voltage VOH V Output Low Voltage VOL V STANDBY CURRENT vs AMBIENT TEMPERATURE STAND...

Page 121: ...aximum Access Time 250ns Low Power Standby and Low Power Operation Standby 5 iW typ Operation 50mW typ Pin Compatible with EPROM BLOCK DIAGRAM PIN ARRANGEMENT HN613286P AO Al A2 A3 A4 AS A6 Address A...

Page 122: ...put High Level Leakage Current hoH CE 0 8V CF 2 4V V 2 4V 5 Mk Output Low Level Leakage Current h L v o v 5 Mk Supply Current In stand by h SS fc iV Vec 5 5V 1 30 pk In operation 7cc art 3 0 1 5 3 0 m...

Page 123: ...75 C t t 20ns Item Symbol min max Unit Read Cycle Time tRC 200 ns Address Access Time tAA 200 ns Chip Select Access Time IACS 200 ns Chip Selection to Output in Low Z tCLZ 10 ns Output Enable to Outp...

Page 124: ......

Page 125: ...lect and Output Enable TTL Compatible Maximum Access Time 250ns Low Power Standby and Low Power Operation Standby OfiW typ Operation 50mW typ Pin Compatible with EPROM BLOCK DIAGRAM Manor Matrja 191 J...

Page 126: ...y state current Vcc 5V Ta 25 C RECOMMENDED AC OPERATING CONDITIONS READ SEQUENCE Vcc 5V 10 Vss OV To 20 to 75 C 20ns Item Symbol min max Unit Read Cycle Time rc 250 ns Address Access Time Ua 250 ns Ch...

Page 127: ...600 bps Post Detection Filter TTL or CMOS Compatible Inputs and Outputs CMOS LSI LOW POWER COMPLEMENTARY MOS UNIVERSAL LOW SPEED 0 600 bps MODEM Jfp jflP L SUFFIX CERAMIC PACKAGE CASE 620 P SUFFIX PL...

Page 128: ...40 1 6 Vql 0 5 lOL 10 53 45 10 36 mA Vql 1 6 15 15 13 35 10 Input Current iPm 15 Vdd l tn 0 00001 0 l A Input Pull Up Resistor Source Current Pin15 V SS Vm 2 4 Vdc Pins 1 2 5 6 10 11 Ip 5 285 250 460...

Page 129: ...ormat to the modulator for conversion to FSK signals for transmission over the telephone network The modulator output is buf fered amplified before driving the 600 ohm telephone line The FSK signal fr...

Page 130: ...an be obtained from the following Motorola publica tions AN 731 Low speed Modem Fundamentals AN 747 Low speed Modem System Design Using the MC6860 8 49 Application Performance ol the MC6860 MODEM FIGU...

Page 131: ...OS or TTL compatible logic level input see TTL pull up disable at a duty cycle of 50 2 that is a square wave resulting from a signal limner RECEIVE DATA RATE Rx Rate Pin 6 The demodulator has been opt...

Page 132: ...MC14412 FIGURE 4 TRANSMIT CARRIER SINEWAVE Rj iCCk V DD bV T Ca l FIGURE 5 TYPICAL TRANSMIT CARRIER FREQUENCY SPECTRUM C 56...

Page 133: ...ckup It can therefore be used as a non volatile RAM cs QT vcc W cs T 1 OSCOUT ADJ T O OSCIN A0 T ai QT A2 W o o U ALARM IJ D2 A3 E g DI RD H 11 DO GND E H WR Features Direct connection to CPU 4 bit bi...

Page 134: ...Terminal connection diagram Block diagram 1Hz 16Hz OSCIN OSCOUT C 58...

Page 135: ...2 5 5 V fXT Oscillation frequency of crystal oscillator 32 768 kHz DC electrical characteristics Ta 0 70 C Vcc 5V 10 unless otherwise specified Symbol I tern Measurement conditions Values Min TYP Max...

Page 136: ...ta delay time after Wft trailing edge TYP Data hold time after WR leasing edge J Max 20 AC electrical characteristics are as follows when Vcc 5v 10 Measuremen conrii t ions Symbol tAC Addresr RD WR de...

Page 137: ...ADJ is set to high when the second counter registers 30 59 t the seconds are set to and the minutes are incremented This ter minal is designed not for edge detection but for level detection A tnin imu...

Page 138: ...x X X El 1 year coun ter C 1 0 year counter MODE ftegi ster Timer EN Al arm EN MODE sel eetor M l MO E Test Register RESET Controller i Test 3 Test 2 Te s t 1 Tinier RESET Tes t F 1Hz ON _ _ _ i IfcH...

Page 139: ...gister X X 6 Al arm day of the wee register X X 7 Alarm 1 doy register B 9 Alarm 10 day register X X X X X Timer EN Test 3 THz 5N X X X X A i2 1 hour 2 4 hour selector Leap year counter X B X X X C X...

Page 140: ...mer EN Alarm EN MODE t Ml elector Timer EN Alarm EM MODE selector MO Mi MO E Test 3 Test 2 Test 1 Timer RESET Test J Test 3 Test 2 Test 1 Test L J 2 Hz ON 16 Hz ON Alarm RESET nil ow 16Hz ON Timer RES...

Page 141: ...O 0 It simultaneously counts with the year counter The 1 2 hour 24 bour selector sets the 12 hotir system when DO and the 24 hour system when DO I PM or AM is selected when Dl in the 10 hour counter i...

Page 142: ...e CS CS WR signal For details see the block diagram o the RP5C01 or Section 4 of these Application Motes READ CVCLE CS H CS Note 2 AO A3 DO D3 RD MO te 2 f XT tAC tRD Jv Notts 2 The RP5CG1 accepts an...

Page 143: ...the 1 6H2 signal Address A3 A2 Al r AG 1 1 1 1 Data 1 r 0 Q G When adjusting with the 1H2 signal Address A3 A2 Al AO U 1 1 1 Data 0 1 0 0 CJSCIN Note 3 CI 10FF 3UPFr C2 30PFr j K lOOkft Crystal oscil...

Page 144: ...d the arrangement shown in Figs 2 a and 2 b below should be adopted The OSCIN terminal is not TTL cfjmp tible but CMOS compa tible 1 With CMOS inverter CMOS MC4069UB RP5C01 Fig 2 a 2 Ki r h TTL invert...

Page 145: ...C CS J OSCOUT ie 30ADJ OSCIN A RD RD RD RD i 9 J Gll l ALARK 03 KuppJ y circuit itJ VA h h E5 16HT r c 15j t See tote 5 on page 55 14J Rp a 1 3 5 Rp Kp 11 12 t r i J Rp i 1 t 5V RD lOOkft 3G0kn Rp 4 7...

Page 146: ...or inpu t terminals However it is recoisni ended that pull up resistors be used for ClS RT and W since if pull down resistors are used for these terminals they wi 1 1 become active when the CPU is on...

Page 147: ...ation Entry conditions D x coordinate 1 40 E y coordinate 1 16 Exit condition none 8D6A PLOT Turn on pixel at specified location Entry conditions D x coordinate 0 239 E y coordinate 0 1 27 Exit condit...

Page 148: ...ock display no scrolling 4F5E V UNLOCK Unlock display scrolling 4F63 w CURSON Turn on cursor 4F68 p CURSOF Turn off cursor 4F6D Q DELLIN Delete line at current cursor position 4F72 M INSLIN Insert a b...

Page 149: ...F8 8 LABEL 9 PRINT OA SHI FT PRINT OB PASTE Wait and get character from keyboard Entry conditions none Exit conditions A character code Carry set if special character reset if norma character F1 F8 r...

Page 150: ...driver when processing F1 F8 keys The strings have maximum length of 1 characters and are terminated by a 80 Hex code If the last character of the string is OR ed with 80 the character will also serv...

Page 151: ...none OUTDLP Print a character expanding tabs to spaces Entry conditions A character to be printed Exit conditions 4FC4 ERAFNK Erase function key display Entry conditions none Exit conditions none 4FA...

Page 152: ...ions HL ph number address Exit conditions none 622B RCVX Check RS232C queue tor characters Entry conditions none Exit conditions A number of characters in queue Z flag set if no data reset if characte...

Page 153: ...AK pressed else reset BAUDST Set Baud rate for RS232 C 86AD Entry conditions 1 1 Baud rate 1 9 M Exit conditions none 86DE INZCOM Initialize RS232 C and Modem Entry conditions H Baud rate 1 9 L USART...

Page 154: ...Name Description Hex Entry Address DATAR Read character from cassette no checksum Entry Conditions none Exit conditions D character from cassette Carry Set if BREAK pressed else reset 88B3 CTON Turn m...

Page 155: ...ditions Carry set if BREAK pressed else reset RAM Files Routines The Directory Table located at F252 contains all file location type and status information Each file is managed by an 1 1 bytes directo...

Page 156: ...s HL address of directory entry for file Exit conditions HL TOP start address of file 6E8C KILASC Kill a text DO file Entry conditions DE file TOP start address HL address of directory entry flag Exit...

Page 157: ...SIC Make tone see owner s manual tor frequency and duration information Entry conditions DE frequency 0 16383 B duration 0 255 Exit conditions none 8BC0 Read system TIME Entry conditions HL address of...

Page 158: ...04 86 SWCC 874 9939 Printed in U S A...