Raisecom Technology Co., Ltd.
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the Master Clock site, or at the Slave Clock site.
If any of the three conditions cannot be met, then both modems shall be set to Master Control and
the first 5 bits will be used to configure the actual bandwidth. Please note that when N=0, the
equipment is working at transparent mode and this bit switch is invalid.
3.2.3 The 7
th
and 8
th
Bits: Timing Resource Option
7
th
bit
8
th
bit
Timing Resource Option
OFF OFF Master
Clock (Internal)
OFF ON V.35
Terminal
Clock
ON OFF Vacant
ON
ON
Slave Clock (follow the link clock)
Users are advised to select the most suitable timing resource according to the connection types in
Chapter 2. When configuring the timing resource, V.35 DTE interface on Routers shall also be
configured. Both TX and RX clock shall be External Clock mode at V.35 interface that connected
with Master/Slave Clock equipment. The TX Clock shall be Internal Clock mode and RX Clock
shall be External Clock mode at the V.35 interface that connected with Terminal Clock equipment.
3.2.4
The Factory Default Setup of SW1: All OFF
Switch 1
st
bit
2
nd
bit
3
rd
bit
4
th
bit
5
th
bit
6
th
bit
7
th
bit
8
th
bit
Default OFF OFF OFF OFF OFF OFF OFF OFF
Details N=31
，
V.35 bandwidth 1984K
Bandwidth
Master
Control
Master Clock
Mode
3.3 Dip-switch SW2 Setup on the Bottom Panel
3.3.1 The 1
st
~ 6
th
Bits Definition
1
st
bit
2
nd
bit
3
rd
bit
4
th
bit
5
th
bit
6
th
bit
Definition
TX CLK
phase
RX CLK
phase
PCM30/31
Option
CRC
function
option
Loop-back
test
Loop-back
option
ON
Negative Negative PCM30 Disable Loop-back
Local
