26
CP52S
COMMERCIAL PROCESSOR
Block Diagram
RELEASE TIME
5 sec.
20 sec.
PRIORITY THRESHOLD
ON
+4 dBu
LINE 1
L
R
LINE 2
L
R
LINE 3
L
R
L
R
INPUT
SELECT
(1 of 4)
7 BAND
EQ
7 BAND
EQ
DUCK
LEVEL
RAMP
LIMIT THRESHOLD
-20 dBu
+20 dBu
MONO
THRESHOLD
PAGE
+
RIGHT
ZONE EXPAND
OUTPUT
EXPAND LEVEL
PAGE
PAGE
PROGRAM
ZONE
PRIORITY
PAGE INPUT
+
-
MIC/LINE
30 dB
PA
D
GAIN TRIM
30 to 60 dB
OL
ACTIVE
100 Hz
7 kHz
PAGING DETECT THRESHOLD
ON
+4 dBu
+5
PAGING LEVEL
LIMIT THRESHOLD
-20 dBu
+20 dBu
PAGE
IN
OUT
A
B
COM
DO
D1
G
Vc
Vr
ZR 1 REMOTE
+5
+5
ZONE LEVEL
REMOTE
RMT
A
B
COM
RMT
PGM SELECT
PORT
DUCKER DEPTH
50 dB
6 dB
RAMP TIME
DUCK
ON
RAMP
DO
D1
PRTY
D1
D0
SELECT
LOGIC
LEVEL
LEVEL
PAGE LEVEL TRACKS ZONE LEVEL
ON
OFF
+15
PHANTOM POWER
ON
OFF
PROGRAM INPUTS
HIGH/LOW CUT FILTER
THRESHOLD
OFF
ZONE OUTPUT
PRIORITY
PROGRAM PRIORITY
ON
OFF
OL
OL
SIG
SIG
DUCKER
-
+
LEFT
-
+
-
Summary of Contents for CP 52S
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