Rastergraf Eclipse3 Series, User Manual

Page 1: ...r s Manual Graphics Boards for PMC PCI and CompactPCI Compatible Computers Rastergraf Inc 1804 P SE First St Redmond OR 97756 541 923 5530 FAX 541 923 6475 web http www rastergraf com Release 2 0 Marc...

Page 2: ...2 5 ECLIPSE3PCI BOARD INSTALLATION 2 10 2 6 ECLIPSE3CPCI BOARD INSTALLATION 2 13 2 7 FINISHING THE INSTALLATION 2 16 2 8 USING AN ECLIPSE3 BOARD IN A PC 2 17 2 9 USING AN ECLIPSE3 BOARD IN A SPARC CPU...

Page 3: ...ay Formats 3 13 Table 3 4 Eclipse3 Video Timing Parameter Request Form 3 17 Table 3 5 I2 C Device Addresses 3 19 Figure 1 1 Borealis Block Diagram 1 4 Figure 1 2 DVI Digital Video Block Digram 1 5 Fig...

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Page 5: ...uters This manual is broken down into four chapters Chapter 1 General Information Chapter 2 Installing the Graphics Board Chapter 3 Programming Devices and Memories Chapter 4 Troubleshooting Chapter 1...

Page 6: ...E mail to support rastergraf com If your problem is monitor related Rastergraf technical support will need detailed information about your monitor Board Revisions This manual applies to the following...

Page 7: ...adio frequency energy which can cause radio interference Rastergraf assumes no liability for any damages caused by such interference Rastergraf products are not authorized for any use as critical comp...

Page 8: ...mmands Commands in code fragments are preceded by the system prompt a percentage sign the standard prompt in UNIX s C shell or the hash mark the standard UNIX prompt for the Super User Keyboard usage...

Page 9: ...The Eclipse3 uses a Rastergraf Borealis 2D 3D 128 bit graphics accelerator It features UVGA compatibility an OpenGL pipeline and can address up to 32 MB of on board SGRAM The Eclipse3 boards are avail...

Page 10: ...tal Output Non interlaced high refresh rate and Sync On Green displays Optional three status LEDs controlled by host software Optional 2 Kb serial EEPROM Optional LM75 thermal sensor Optional 3 3V Reg...

Page 11: ...gnification filtering Full OpenGL Texture Decal Blend and Modulation Modes RGB Modulation Lighting Effects Support Palletized Textures 1 2 4 and 8 bit Support Non Palette Textures 8 16 and 32 bit Floa...

Page 12: ...orealis to repetitively execute strings of commands The Borealis supports a local frame buffer with up to 32 MB SGRAM using a 128 bit wide data bus The frame buffer may be accessed as linear buffers t...

Page 13: ...hannels send data at 1 65 Gbps per channel Connections to the Eclipse3 are made through the front DVI I connector Figure 1 2 DVI Digital Video Block Digram 1 2 3 Software Support Rastergraf software s...

Page 14: ...A Control Logic 16 32 MB Display Memory R G B H V 128 Display List Processor Host PCI Bus PanelLink Digital Output PCI PMC Host Bus Interface 33 66 MHz PCI 2 1 32 bit Peritek Borealis 3D Graphics Acce...

Page 15: ...CompactPCI Hot Swap Infrastructure Interface Specification PICMG 2 12 R1 0 standards and other information are available from PICMG Web Page https www picmg org index stm The PCI Local Bus 2 2 Specif...

Page 16: ...lock Display Memory Display memory is 16 MB or 32 MB of 128 bits word byte addressable no wait state SGRAM 16 MB of SGRAM gives eight pages of 1600 x 1200 using 8 bit pixels four pages using 16 bit pi...

Page 17: ...en a DVI display is not desired or available Composite Video Signal A jumper can be installed to select Sync On Green operation on boot up The signal has the following approximate values 1 Volt peak t...

Page 18: ...60 Hz 75 KHz 194 4 MHz Table 1 3 Eclipse3 VGA Windows Platform Display Timing Specifications Active Display Analog DVI VESA Format Bits per Pixel Vertical Refresh Horizontal Refresh Pixel Clock 640 x...

Page 19: ...nterrupts The Borealis can interrupt the PCI bus on the INTA line Bus Loading One PCI 2 1 compatible load Module Size PMC IEEE 1386 2001 149 mm x 74 mm 32 bit 33 66 MHz J1 J2 CompactPCI PICMG 2 0 Rev...

Page 20: ...real time temperature read back Ruggedization Option Rastergraf offers semi ruggedized versions of the Eclipse3 boards include a MIL compliant silicone or acrylic conformal coating and extended temper...

Page 21: ...ing 0 to 100 condensing 0 to 100 condensing 0 to 100 condensing Vibration Sine 1 2 g peak 15 2 kHz 2 g peak 15 2 kHz 10 g peak 15 2 kHz 10 g peak 15 2 kHz 10 g peak 15 2 kHz 10 g peak 15 2 kHz Vibrati...

Page 22: ...connector This connector supplies RGBHV Red Green Blue and Horizontal and Vertical sync DDC DDA monitor control signals as well as DVI digital video output An adapter connector Molex 88741 8700 availa...

Page 23: ...2 9 2 concerning composite sync on green and RGBHV video out modes If you have problems please contact Rastergraf for assistance The R G and B video outputs are driven by the Borealis graphics control...

Page 24: ...round Circuit Ground 7 Green Ground Circuit Ground 8 Blue Ground Circuit Ground 9 Fused 5 Volts 25A max 10 Sync Ground Circuit Ground 11 Ground Circuit Ground 12 DDCDA Twisted Pair with GND to pin 10...

Page 25: ...VGA connector There is no split off for DVI You can also get cables and or adapters that provide both analog and digital or just analog or digital Rastergraf strongly urges you to obtain commercially...

Page 26: ...3 3V AD20H 28 29 AD19H VCC 5V 30 29 AD18H GND 30 31 byp Vio AD17H 32 31 AD16H C BE2L 32 33 FRAMEL GND 34 33 GND n c 34 35 GND IRDYL 36 35 TRDYL VDD 3 3V 36 37 DEVSELL VCC 5V 38 37 GND STOPL 38 39 GND...

Page 27: ...PPCIRSTL GND 15 47 PAD11H PAD12H 47 16 byp Vio PPCICLK 16 48 GND PAD10H 48 17 PCIGNTL GND 17 49 PAD09H n c 49 18 GND PCIGNTL 18 50 keyway keyway 50 19 n c byp Vio 19 51 keyway keyway 51 20 PAD30H PAD3...

Page 28: ...ND 73 74 n c n c 74 75 byp Vio n c 75 76 n c GND 76 77 n c n c 77 78 GND n c 78 79 n c byp Vio 79 80 n c n c 80 81 GND n c 81 82 n c GND 82 83 n c n c 83 84 byp Vio n c 84 85 n c GND 85 86 n c n c 86...

Page 29: ...eyway 12 keyway 12 keyway 12 keyway 13 keyway 13 keyway 13 keyway 13 keyway 13 keyway 14 keyway 14 keyway 14 keyway 14 keyway 14 keyway 15 VDD 3 3V 15 FRAME 15 IRDY 15 GND 15 TRDY 16 DEVSEL 16 GND 16...

Page 30: ...VIO GND 10 GND GND GND 11 GND GND VIO GND 12 GND GND GND 13 GND GND VIO GND 14 GND GND GND 15 GND GND RIO_BLU RIO_RED GND 16 GND GND GND 17 GND GND RIO_GRN RIO_DDAH GND 18 GND GND GND 19 GND GND GND G...

Page 31: ...GB with sync on green see note below Switchable Termination for monitor loopthrough Height pincushion width phase and position controls Autotracking horizontal and vertical synchronization See tables...

Page 32: ...ore information about this and other special configurations Table 1 6 Eclipse3 Software Operating System Rastergraf Software Version OpenGL and or DirectX DVI SOG BIOS Solaris 2 6 10 DDX 3 0 no yes FC...

Page 33: ...teps involved in getting your Rastergraf Graphics board to work in your system Unpack and install the Rastergraf graphics board Install the software This chapter shows you how to install the Rastergra...

Page 34: ...e ready to install it It is preferable to wear a grounded wrist strap whenever handling computer boards Some operating systems require that you reboot your system after installing a device driver beca...

Page 35: ...d or BIOS while booting up there aren t any address jumpers The address settings are programmable and are set up by the Eclipse3 software as a result of information supplied by the OS at boot time Ref...

Page 36: ...Sync On Green SOG The firmware can determine the need to run FCode or VGA and if the DVI monitor is plugged in it will select DVI mode without user intervention However a separate jumper is needed to...

Page 37: ...lipse3CPCI or Eclipse3PCI Note Older VME host or carrier boards may not supply 3 3V to the PMC connectors and the Eclipse3 PMC boards require both 3 3V and 5V By special order Rastergraf can supply th...

Page 38: ...g Your Peritek Graphics Board Figure 2 1 Jumper Locations for the Fab Rev 1 2 Eclipse3PMC Board JP101 Sync On Green Jumper Fab Revision Number JP203 Optional Local 3 3V Power JP201 VGA Sub class Devic...

Page 39: ...cs PMC board is a Universal PMC PCI device and can be plugged into a PMC port which uses either 5V or 3 3V signaling 3 Take care to optimize airflow by blocking off unused slots in the card cage and a...

Page 40: ...Rastergraf 2 8 Installing Your Peritek Graphics Board Figure 2 3 Installation of a PMC Module into the PMB C PMC Slot 1 PMC Slot 0...

Page 41: ...mounting screws two near the front and two near the PMC connectors Note Sometimes the graphics board front panel can hang up going into the carrier front panel hole This can be because there is a lit...

Page 42: ...V regulator installed Please contact Rastergraf for assistance Installing the PCI Graphics Board Note Refer to Section 2 3 3 for the settings for JP101 JP201 and JP233 1 Shut down the operating system...

Page 43: ...Rastergraf Installing Your Peritek Graphics Board 2 11 Figure 2 5 Jumper Locations for the Eclipse3PCI Board JP101 Flash Bank Fab Revision Number JP201 VGA JP233 Local 3 3 32 64 bit PCI slot...

Page 44: ...he computer chassis Remove the card slot blocking plate from the chassis Then remove the graphics board from its anti static bag and immediately slide it into the slot Figure 2 6 Installation of a PCI...

Page 45: ...r supply Unless internal AC wiring is exposed leave the power cord plugged in so as to ground the computer chassis You can easily get shocked ruin computer parts or both unless you turn off the power...

Page 46: ...Rastergraf 2 14 Installing Your Peritek Graphics Board Figure 2 7 Jumper Locations for the Eclipse3CPCI Board JP102 Frame Chassis Ground Fab Revision Number JP101 Flash Bank JP201 VGA...

Page 47: ...oard 4 Wear a grounded wrist strap Touch a metal part of the computer chassis remove the graphics board from its anti static bag and immediately slide it into the slot Figure 2 8 Installing a CompactP...

Page 48: ...n 2 7 2 Checking your Display Note The Eclipse3 boards can supply 3 Wire RGB with sync on green BNC connectors or 5 Wire Video RGBHV VGA connector Rastergraf software defaults to 5 Wire Video NO sync...

Page 49: ...e VGA controller and you want to use the Rastergraf board as the system display you may have a problem If the BIOS starts up using the built in VGA you may be able to disable it with a BIOS setting Ot...

Page 50: ...n will not be disabled but if a DVI monitor is later connected it may not display properly During boot the BIOS will display a message screen for 10 seconds before relinquishing control back to the sy...

Page 51: ...pixel SVGA VESA 0x0105 1024 x 768 8 bits per pixel UVGA VESA 0x0107 1280 x 1024 8 bits per pixel SXGA VESA 0x0110 640 x 480 15 bits per pixel VGA VESA 0x0111 640 x 480 16 bits per pixel VGA VESA 0x011...

Page 52: ...wrong one swap cables or turn power off and swap the boards positions If your system has a non removable VGA controller and you want to use the Rastergraf board as the system display you may have a p...

Page 53: ...ection makes use of the OpenBoot nvedit utility to change the default settings for the Rastergraf FCode that are maintained in the nvramrc file by OpenBoot NVEDIT Commands Ctrl N Go to the next line C...

Page 54: ...SXGA 6 800 x 600 60 Hz SVGA 7 800 x 600 75 Hz SVGA 8 640 x 480 60 Hz VGA 9 640 x 480 75 Hz VGA a 1152 x 900 60 Hz Sun old b 1152 x 900 75 Hz Sun old c 1600 x 1200 60 Hz UXGA d 1920 x 1200 60 Hz WUXGA...

Page 55: ...erved 6 Sync on Green negative negative yes yes 7 Sync on Green negative negative no yes I initial system default If you do not wish to change the display mode please skip to the next section To chang...

Page 56: ...receive 1 mode constant eclipse3 console sync if instead you receive 1 but no text it means that the console sync is not set type return receive 2 if instead you receive 2 and some text type ctrl k t...

Page 57: ...ed by the BIOS Once you have installed the Windows NT 2K XP multihead drivers and reboot all screens will be initialized as the OS boots In the case of X Windows your monitor should display a uniform...

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Page 59: ...t is intended to supply information unique to the board or to the application of a particular chip Section 1 3 provides a list of appropriate publications that include manufacturer s data sheets and m...

Page 60: ...pts Because the Eclipse3 is mostly an assembly of black box parts there isn t a lot of external logic that has to be documented Thus the following sections don t actually provide much programming info...

Page 61: ...ndering After a sequence of commands and parameters are written Borealis executes the selected command without any further host processor intervention 3 2 2 Host Bus Interface The Host Bus Interface p...

Page 62: ...ler Memory Controller Internal VGA Internal RAMDAC Figure 3 1 Borealis Block Diagram Host Bus Interface CRT Controller Memory Controller PXD 127 0 CJ 15 0 BLANK HSYNC AD 31 0 CAS HBCLK RST CNTRL 6 0 A...

Page 63: ...herency during any access to the local buffers for optimal performance 3 2 5 Drawing Engine The Drawing Engine provides all the required logic to implement BITBLT LINE LINE_3D TRIAN_3D and HOST XFER c...

Page 64: ...which generates interrupts to the Host is also provided This is useful for synchronizing bit map copies CRT Controller also provides display refresh data for the internal RAMDAC 3 2 8 Memory Controlle...

Page 65: ...memory controller and the other for the pixel data Feature Summary 250 MHz operation 128 bit 64 bit multiplexer from the pixel FIFO Fine grained PLL programming optimizes display Pixel re synchroniza...

Page 66: ...d then converted to 16 bit 2 s complement integers In all cases no overflows will be detected or reported Care must be taken for drawing operations not to exceed the 16 bit coordinate space The displa...

Page 67: ...s Please contact Rastergraf if it is necessary to change a value Table 3 1 Borealis Configuration Settings CJ In Out Function Default 31 in out 16 MB video memory 30 in PCIBAR 0 1 address size 32 MB v...

Page 68: ...ence The pixel frequency can be set to between 25 MHz and 250 MHz MCLK is the Borealis memory clock for the Borealis memory controller and SGRAM interface and is generated by a independent PLL interna...

Page 69: ...e to be repeated several times during the raster line time to keep the FIFO filled The SGRAM is available for random access operations at all other times There is a small additional overhead time for...

Page 70: ...ained it is necessary to maintain a few extra control bits for supplementary features Using the Micrel MIC74 I2 C 8 bit I O register the graphics board supports an auxiliary register All bits come up...

Page 71: ...rovided in a configuration file for Rastergraf s PX Windows server Does your Display have a Green Cast to it By default the Eclipse3 supplies video in separate five wire video RGBHV video format If yo...

Page 72: ...ou specify vertical frequency in Hz vertical blanking in milliseconds ms vertical front porch in ms vertical sync width in ms horizontal blanking in microseconds us horizontal front porch in us horizo...

Page 73: ...rther Changing the horizontal frequency will also affect the vertical frequency Decreasing the horizontal frequency will generally result in a wider picture To change the horizontal position To shift...

Page 74: ...e image aspect ratio remains the same 2 Change the vertical frequency but keep the horizontal the same Decreasing the vertical frequency will result in a shorter image increasing it will result in a t...

Page 75: ...ven in pixel units if given or time units Horizontal Pixels per Line Displayed____________________ Pixel Time or Frequency optional ____________________ Horizontal Total Line Time or Frequency________...

Page 76: ...e chip entirely useless Signature registers in the RAMDAC can be are used to confirm that a test pattern in display memory will pass correctly through the Borealis all the way to the DAC inputs This i...

Page 77: ...ination of device internal bits bits 4 7 and usually three pins that are wired by the board designer bits 1 3 Bit 0 is used to denote a Read 1 or Write 0 operation Because the Eclipse3 board serial EE...

Page 78: ...ug Detection for a variety of power management options You can obtain the data sheet for the THC63DV164 from the technical document section on the Rastergraf web site Features Scaleable Bandwidth 25 1...

Page 79: ...D19 R0 3 R1 3 R2 3 D18 R0 2 R1 2 R2 2 D17 R0 1 R1 1 R2 1 D16 R0 0 R1 0 R2 0 D15 G0 7 G1 7 G2 7 D14 G0 6 G1 6 G2 6 D13 G0 5 G1 5 G2 5 D12 G0 4 G1 4 G2 4 D11 G0 3 G1 3 G2 3 D10 G0 2 G1 2 G2 2 D9 G0 1 G...

Page 80: ...equivalent 2 Kb 256 bytes I2 C Serial Electrically Erasable Programmable Read Only Memory EEPROM The programming of the Serial EEPROM is done through control lines on the Borealis chip Rastergraf rese...

Page 81: ...ing Introduction This chapter contains information which should assist you in tracking down installation and functional problems with your board 4 1 General procedures 4 2 Dealing with the PCI bus 4 3...

Page 82: ...ine this A typical Eclipse3 will draw a total of less than 1 amps at 5 and 3 3 Volts When attempting to verify that the power supply is working properly it is not unusual to unplug everything and meas...

Page 83: ...pse3 graphics board in a PowerPC based system it is vital to ensure that Rastergraf can vouch for the board s operation before you order the board Otherwise you may go crazy trying to figure out why i...

Page 84: ...ble should also be included Customer should prepay shipping charges to the factory Rastergraf will prepay return shipping charges to the customer Repair work is normally done within ten working days f...

Page 85: ...ription 3 3 initial testing 2 2 Internal RAMDAC 3 4 Internal VGA 3 4 interrupts 3 22 Linear windows controller description 3 5 Linux 0 1 3 1 LM75 1 11 1 12 3 18 3 19 Maintenance 4 3 Memory controller...