RTL8366/8369 & RTL8212
Layout Guide
RTL8366/8369 & RTL8212 Layout Guide
11
Track ID: JATR-1076-21 Rev. 1.1
3.3.
Clock Circuit
•
Place the crystal as close to the RTL8366/8369 as possible.
•
Surround the clock with ground trace to minimize high-frequency emissions.
•
Use only one 1.5K pull up external resistance to 3.3V for MDIO.
•
Keep the MDC trace away from the other signals, to avoid unnecessary interference.
•
Keep clearance area under the crystal or OSC component.
•
Don’t let the clock trace pass over a gap in the ground plane.
3.4.
Power Planes
•
When designing a 4-layer PCB layout, divide the power plane into 3.3V_MAC, 3.3V_PHY, 1.8V
and 1.2V.
•
Use 0.1
µ
F decoupling capacitors and bulk capacitors between each power plane and ground plane.
3.5.
Ground Planes
•
Keep the system ground region as one continuous, unbroken plane that extends from the primary
side of the transformer to the rest of the board.
•
Place a moat (gap) between the system ground and chassis ground.
•
Ensure the chassis ground area is voided at some point such that no ground loop exists on the
chassis ground area.
