RTL8366/8369 & RTL8212
Layout Guide
RTL8366/8369 & RTL8212 Layout Guide
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Track ID: JATR-1076-21 Rev. 1.1
1.
General Description
This document provides detailed design and layout guidelines to achieve the best performance when
implementing a 4-layer board design with the RTL8366/8369 10/100/1000Mbps switch controller, and
the RTL8212 dual port 10/100/1000Mbps Ethernet transceiver.
The RTL8366 and RTL8369 are 128-pin, ultra-low-power, high-performance 5/8-port Gigabit Ethernet
switches, with one extra GMII/MII/RGMII port for specific applications. They integrate all the functions
of a high speed switch system; including SRAM for packet buffering, non-blocking switch fabric, internal
register management, and an embedded 8051 into a single 0.15µm CMOS device. Only a 25MHz crystal
is required; an optional EEPROM is offered for internal register configuration.
The 6/9th port of the RTL8366/8369 implements a GMII/MII/RGMII interface for connecting with an
external PHY or MAC in specific applications. This interface could be connected to an external CPU or
RISC in 1 WAN + 4 LAN or 1 WAN + 8 LAN Router applications.
The RTL8212 integrates dual independent Gigabit Ethernet transceivers into a single 0.13µm CMOS
device and includes the PCS, PMA, and PMD sub-layers. They perform encoding/decoding, clock/data
recovery, digital adaptive equalization, echo cancellers, cross-talk elimination, line driver, as well as all
other required support circuit functions.
