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Redpine Signals, Inc. Proprietary and Confidential
Page 37
2.2.2
SDIO mode Interface Schematic (Input supply – 1.8V)
R10
100K
RESET_N
C13
0.1uF
H os t M C U may direc tly drive the RE SE T _N
pin of the module as s hown below.
OPTION-3
OPTION-1
RESET_N
MCU pin
driving
RESET_N
HOST MCU
RS9113 based
Module
R13
10K
RESET_N
C14
8.2nF
R9
1M
R12
100K
U2
MAX6415
VCC
5
SRT
4
RESETn
1
GND
2
RESET IN
3
C12
0.1uF
R
11
1M
SW
1
1
2
RESET Circuitry
OPTION-2
Title
Size
Document Number
Rev
Date:
Sheet
of
RS9113 based Module without integrated antenna -SDIO-1.8V
1
1
GPIO_16
R8
820E
LED Indication
D1
LED
VDD_EXT
VDD_EXT
VDD_EXT
Note:
R23 should be mounted for USB Enumeration
R23 should not be mounted for USB_CDC Enumeration
BUCK/BOOST SECTION
R16
100K
R17
100K
GPIO_4
GPIO_3
R18
100K
GPIO_5
R19
100K
DVDD33
GPIO_6
DVDD33
DVDD33
DVDD33
SDIO_D2
SDIO_CMD
SDIO_CLK
SDIO_D3
VIN_SDIO
SDIO_D0
SDIO_D1
N O T E :
P ull up res is tors s hould be pres ent on SDI O C M D & SDI O Data lines ac c ording
to the s ec tion 6 .6 .5 of SD phys ic al layer s pec ific ation, vers ion 2 .0 0
N O T E :
R1 4 * * value s hould be adjus ted bas ed
on driver output impedanc e and P C B
T rac e I mpedanc e,,(3 3 E is N ominal)
J2
SDIO Interface Connector
CD/DAT3
1
CMD
2
VSS1
3
VDD
4
CLK
5
VSS2
6
DAT0
7
DAT1
8
DAT2
9
C5
10uF(0805)
R14**
R15
100K
DVDD33
VRF33
GPIO_16
VIN_SDIO
DVDD33
R21
100K
R22
100K
R23
4.7K(NP)
R24
4.7K(NP)
Note:
Y1 is used for accurate w akeup time
R5
100K
R7
100K
U1
RS9113 based Module
GN
D
1
VIN_MOD
49
GPIO_21
81
GPIO_16
28
GPIO_15
29
PDN
58
GPIO_18
82
GPIO_17
84
SDIO_DATA2
26
SDIO_CLK
25
SDIO_DATA3
80
SDIO_DATA1
79
SDIO_CMD
24
SDIO_DATA0
78
USB_VDDP
77
USB_VBUS
16
GND
20
USB_DP
18
USB_ID
19
USB_VDDD
15
GPIO_5
13
NC
46
WURX
2
GN
D
42
RF_OUT_2
32
NC
39
GN
D
33
GN
D
85
RF_OUT_1
37
GN
D
34
GN
D
35
GN
D
36
NC
89
GN
D
38
GPIO_19
21
GPIO_11
8
GPIO_12
98
GN
D
51
GN
D
90
VRF33
53
GPIO_9
7
GPIO_14
9
GPIO_10
6
GPIO_13
71
XTAL_32Khz_N
5
XTAL_32Khz_P
4
VBATT
100
GND
48
NC
56
ULP_GPIO_2
99
RESET_N
74
VDD33
59
JP1
70
JP0
69
BOOTLOAD_EN
41
HOST_SEL_1
55
HOST_SEL_0
60
BBP_LMAC_VDD_12
91
GPIO_8
83
VOUTLDOP3
66
NC
31
USB_DN
17
USB_VDDS
23
SDIO_VDD_18_33
27
GPIO_3
22
GPIO_4
12
GPIO_6
76
GPIO_0
75
GPIO_1
11
GPIO_2
10
GN
D
47
NC
54
GN
D
43
GN
D
45
ULP_GPIO_1
68
HOST_BB_EN
94
ULP_GPIO_0
3
AUX_DAC_OUT
93
JP2
96
JNC
97
GN
D
86
AUX_ADC_IN0
65
BOOT_MODE_0
40
GN
D
44
GPIO_7
30
VOUTLDOP1A
63
VOUTLDOP1
92
USB_VDDA
14
NC
72
EXT_PA_ON
64
GN
D
57
GN
D
87
GN
D
88
GN
D
101
DVDD33
50
NC
61
VRF33
52
ULP_ANAGPI
73
GN
D
67
NC
95
NC
62
SDIO_D1
VIN_SDIO
SDIO_CLK
SDIO_CMD
SDIO_D3
SDIO_D2
RESET_N
R2
1K
R6
100K
C6
20pF(NP)
Y 1
MC-146(NP)
1
4
C7
20pF(NP)
R3
1K
R4
1K
SDIO_D0
NO POPULATE
C1
2.2uF
without integrated antenna
GPIO_1
GPIO_0
C4
2.2uF
FB9
BEAD
C23
0.1uF
VIN_SDIO
FB5
BEAD
VOUT_3V3
U3
TPS63001
L1
4
L2
2
VIN
5
VOUT
1
VINA
8
EN
6
PS/SY NC
7
GND
9
PGND
3
FB
10
GND
11
L2
2.2uH
C
15
10uF
(0805)
C
16
10uF
(0805)
FB10
BEAD
ANA3V3
C26
1uF
FB11
BEAD
Power Supply Filter Section
VDD_EXT
C11
0.1uF
FB8
BEAD
VOUT_3V3
DVDD33
C9
0.1uF
VRF33
C8
47uF(CASE B)
FB6
BEAD
C17
2.2uF
FB7
BEAD
C18
22uF(CASE B)
Tantalum
C24
0.1uF
C19
0.1uF
L1
4.7uH
VINMOD
C25
1uF
Note: Ensure a reset assertion time of 20ms.
Note:
R15, R21, R22 should be mounted
only w hen ULP not USED
C21
0.1uF
VINMOD
C3
10uF(0805)
ANA3V3
C2
8.2pF
50 Ohm RF line
Redpine Signals Confidential
Z1 , Z2 , Z3 form the tuning network for
matc hing the impedanc e of the A ntenna.
T he values depend upon the layout. I n c as e
tuning network is not implemented Z1
s hould be plac ed as 8 .2 pF as default
ANT1
ANT1
1
ANT2
2
Z3
TBD
Z2
TBD
Z1
TBD
Tuning Netw ork
J1
MM8430-2610RA1
ANTIN
3
ANTOUT
4
GN
D
1
GN
D
2
GN
D
5
GN
D
6
M ic rowave s witc h is us ed for evaluating the
s tandalone T rans mit/Rec eive performanc e of the
WLA N module by providing direc t c onnec tivity to
Signal generator/A nalyzer through RF c able
Place Z1-Z3 Close together
and near to ANT1
Mating Connector Part No::MXHS83QH3000