Redpine Signals, Inc. Proprietary and Confidential
Page 52
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2.2.7
UART mode Interface Schematic
OPTION-1
RESET_N
C14
8.2nF
R9
1M
R12
100K
U2
MAX6415
VCC
5
SRT
4
RESETn
1
GND
2
RESET IN
3
C12
0.1uF
R
11
1M
SW
1
1
2
RESET Circuitry
OPTION-2
Title
Size
Document Number
Rev
Date:
Sheet
of
RS9113 based Module without integrated antenna -UART
1
1
Rev0.0
VDD_EXT
VDD_EXT
C2
8.2pF
50 Ohm RF line
Redpine Signals Confidential
Z1 , Z2 , Z3 form the tuning network for
matc hing the impedanc e of the A ntenna.
T he values depend upon the layout. I n c as e
tuning network is not implemented Z1
s hould be plac ed as 8 .2 pF as default
ANT1
ANT1
1
ANT2
2
Z2
TBD
Z3
TBD
Tuning Netw ork
Z1
TBD
J1
MM8430-2610RA1
ANTIN
3
ANTOUT
4
GN
D
1
GN
D
2
GN
D
5
GN
D
6
M ic rowave s witc h is us ed for evaluating the
s tandalone T rans mit/Rec eive performanc e of the
WLA N module by providing direc t c onnec tivity to
Signal generator/A nalyzer through RF c able
Place Z1-Z3 Close together
and near to ANT1
Mating Connector Part No::MXHS83QH3000
Note:
Host select pull-dow n resistors
are required only in
WiSeConnect/Connect-io-n
module based designs.
R8
820E
LED Indication
GPIO_16
D1
LED
VDD_EXT
Note:
If the device is configured in UART Mode
only,connect
SDIO_CLK,SDIO_CMD,SDIO_DATA1,SDIO_DATA2 to
ground through a 51K pull dow n resistor
UART Circuitry
C15
0.1uF
C16
0.1uF
UART1-TX
DB9-TXD
DB9-RXD
C20
0.1uF
UART1-RX
U3
MAX3232CDBR
GND
15
VCC
16
R1IN
13
R2IN
8
T2IN
10
T1IN
11
C1+
1
C1-
3
C2+
4
C2-
5
R1OUT
12
R2OUT
9
T1OUT
14
T2OUT
7
V+
2
V-
6
C22
0.1uF
C21
0.1uF
DB9-TXD
DB9-RXD
R16
0E(NP)
DB9_FEMALE
DB9-RTS
DB9-CTS
DB9-RTS
DB9-CTS
UART1-CTS
UART1-RTS
P1
5
9
4
8
3
7
2
6
1
VDD_EXT
C170
0.1uF
J13
1
2
3
C171
100uF(CaseB)
DC Source
VIN_33
R19
100K
Note:
R26 should be mounted for USB Enumeration
R26 should not be mounted for USB_CDC Enumeration
GPIO_4
R20
100K
GPIO_5
GPIO_3
R21
100K
DVDD33
GPIO_6
R22
100K
DVDD33
DVDD33
DVDD33
R23
100K
DVDD33
GPIO_16
DVDD33
VIN_33
VRF33
R24
100K
R25
100K
R26
4.7K(NP)
R27
4.7K(NP)
R5
100K
Note:
Y1 is used for accurate w akeup time
R7
100K
U1
RS9113 based Module
GN
D
1
VIN_MOD
49
GPIO_21
81
GPIO_16
28
GPIO_15
29
PDN
58
GPIO_18
82
GPIO_17
84
SDIO_DATA2
26
SDIO_CLK
25
SDIO_DATA3
80
SDIO_DATA1
79
SDIO_CMD
24
SDIO_DATA0
78
USB_VDDP
77
USB_VBUS
16
GND
20
USB_DP
18
USB_ID
19
USB_VDDD
15
GPIO_5
13
NC
46
WURX
2
GN
D
42
RF_OUT_2
32
NC
39
GN
D
33
GN
D
85
RF_OUT_1
37
GN
D
34
GN
D
35
GN
D
36
NC
89
GN
D
38
GPIO_19
21
GPIO_11
8
GPIO_12
98
GN
D
51
GN
D
90
VRF33
53
GPIO_9
7
GPIO_14
9
GPIO_10
6
GPIO_13
71
XTAL_32Khz_N
5
XTAL_32Khz_P
4
VBATT
100
GND
48
NC
56
ULP_GPIO_2
99
RESET_N
74
VDD33
59
JP1
70
JP0
69
BOOTLOAD_EN
41
HOST_SEL_1
55
HOST_SEL_0
60
BBP_LMAC_VDD_12
91
GPIO_8
83
VOUTLDOP3
66
NC
31
USB_DN
17
USB_VDDS
23
SDIO_VDD_18_33
27
GPIO_3
22
GPIO_4
12
GPIO_6
76
GPIO_0
75
GPIO_1
11
GPIO_2
10
GN
D
47
NC
54
GN
D
43
GN
D
45
ULP_GPIO_1
68
HOST_BB_EN
94
ULP_GPIO_0
3
AUX_DAC_OUT
93
JP2
96
JNC
97
GN
D
86
AUX_ADC_IN0
65
BOOT_MODE_0
40
GN
D
44
GPIO_7
30
VOUTLDOP1A
63
VOUTLDOP1
92
USB_VDDA
14
NC
72
EXT_PA_ON
64
GN
D
57
GN
D
87
GN
D
88
GN
D
101
DVDD33
50
NC
61
VRF33
52
ULP_ANAGPI
73
GN
D
67
NC
95
NC
62
DVDD33
RESET_N
R2
1K
R6
100K
C6
20pF(NP)
Y 1
MC-146(NP)
1
4
ANA3V3
C7
20pF(NP)
FB10
BEAD
R3
1K
C26
1uF
R4
1K
FB11
BEAD
C1
2.2uF
Power Supply Filter Section
NO POPULATE
without integrated antenna
VDD_EXT
GPIO_0
GPIO_1
C11
0.1uF
VIN_33
FB8
BEAD
C4
2.2uF
FB9
BEAD
C9
0.1uF
C23
0.1uF
VRF33
DVDD33
C8
47uF(CASE B)
C25
0.1uF
FB6
BEAD
C17
2.2uF
Note:
R23, R24, R25 should be mounted
only w hen ULP not USED
VINMOD
C3
10uF(0805)
FB7
BEAD
C18
22uF(CASE B)
ANA3V3
Tantalum
C24
0.1uF
VINMOD
L1
4.7uH
C19
0.1uF
C27
1uF
H os t M C U may direc tly drive the RE SE T _N
pin of the module as s hown below.
OPTION-3
R13
10K
HOST MCU
RESET_N
MCU pin
driving
RESET_N
Note: Ensure a reset assertion time of 20ms.
R15
4.7K
R14
4.7K
R17
51K
R10
100K
RESET_N
C13
0.1uF
Figure 20: UART mode Interface Schematic