CHAPTER 6 CLOCK GENERATOR
Page 112 of 920
Figure 6 - 9 Format of Peripheral enable register 0 (PER0) (3/3)
Address: F00F0H
After reset: 00H
Symbol
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
Control of timer array unit 1 input clock supply
0
Stops input clock supply.
• SFR used by timer array unit 1 cannot be written.
• Timer array unit 1 is in the reset status.
1
Enables input clock supply.
• SFR used by timer array unit 1 can be read and written.
Control of timer array unit 0 input clock supply
0
Stops input clock supply.
• SFR used by timer array unit 0 cannot be written.
• Timer array unit 0 is in the reset status.
1
Enables input clock supply.
• SFR used by timer array unit 0 can be read and written.
Summary of Contents for RL78/G1H
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