CHAPTER 6 CLOCK GENERATOR
Page 138 of 920
6.6.7
Conditions before clock oscillation is stopped
The following lists the register flag settings for stopping the clock oscillation (disabling external clock input) and
conditions before the clock oscillation is stopped. Check the condition before stopping clock before stopping the
clock.
Table 6 - 13 Conditions Before the Clock Oscillation Is Stopped and Flag Settings
Clock
Conditions Before Clock Oscillation Is Stopped
(External Clock Input Disabled)
Flag Settings of SFR Register
High-speed on-chip oscillator
clock
MCS = 1 or CLS = 1
(The CPU is operating on a clock other than the high-
speed on-chip oscillator clock.)
HIOSTOP = 1
X1 clock
MCS = 0 or CLS = 1
(The CPU is operating on a clock other than the
high-speed system clock.)
MSTOP = 1
External main system clock
XT1 clock
CLS = 0
(The CPU is operating on a clock other than the
subsystem clock.)
XTSTOP = 1
External subsystem clock
Summary of Contents for RL78/G1H
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