CHAPTER 7 TIMER ARRAY UNIT
Page 177 of 920
7.5.2
Start timing of counter
Timer count register mn (TCRmn) becomes enabled to operation by setting of TSmn bit of timer channel start
register m (TSm).
Operations from count operation enabled state to timer count Register mn (TCRmn) count start is shown in Table
7 - 4.
Table 7 - 4 Operations from Count Operation Enabled State to Timer count Register mn (TCRmn) Count Start
Timer operation mode
Operation when TSmn = 1 is set
Interval timer mode
No operation is carried out from start trigger detection (TSmn=1) until count clock
generation.
The first count clock loads the value of the TDRmn register to the TCRmn register and the
subsequent count clock performs count down operation (see
Event counter mode
Writing 1 to the TSmn bit loads the value of the TDRmn register to the TCRmn register.
If detect edge of TImn input, the subsequent count clock performs count down operation
(see
(2) Operation of event counter mode
).
Capture mode
No operation is carried out from start trigger detection until count clock generation.
The first count clock loads 0000H to the TCRmn register and the subsequent count clock
performs count up operation (see
(3) Operation of capture mode (input pulse
).
One-count mode
The waiting-for-start-trigger state is entered by writing 1 to the TSmn bit while the timer is
stopped (TEmn = 0).
No operation is carried out from start trigger detection until count clock generation.
The first count clock loads the value of the TDRmn register to the TCRmn register and the
subsequent count clock performs count down operation (see
).
Capture & one-count mode
The waiting-for-start-trigger state is entered by writing 1 to the TSmn bit while the timer is
stopped (TEmn = 0).
No operation is carried out from start trigger detection until count clock generation.
The first count clock loads 0000H to the TCRmn register and the subsequent count clock
performs count up operation (see
(5) Operation of capture & one-count mode
Summary of Contents for RL78/G1H
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