CHAPTER 7 TIMER ARRAY UNIT
Page 206 of 920
Remark
m: Unit number (m = 0), n: Channel number (n = 3)
Figure 7 - 54 Operation Procedure When Input Pulse Interval Measurement Function Is Used
Remark
m: Unit number (m = 0), n: Channel number (n = 3)
Software Operation
Hardware Status
TAU
default
setting
Input clock supply for timer array unit m is stopped
(Clock supply is stopped and writing to each register
is disabled.)
Sets the TAUmEN bit of peripheral enable register m
(PER0) to 1.
Input clock supply for timer array unit m is supplied.
Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
Sets timer clock select register m (TPSm).
Determines clock frequencies of CKm0 to CKm3.
Channel
default
setting
Sets the corresponding bit of the noise filter enable
registers 1 (NFEN1) to 0 (off) or 1 (on).
Sets timer mode register mn (TMRmn) (determines
operation mode of channel).
Channel stops operating.
(Clock is supplied and some power is consumed.)
Op
eration is resume
d.
Operation
start
Sets TSmn bit to 1.
The TSmn bit automatically returns to 0 because it is a
trigger bit.
TEmn = 1, and count operation starts.
Timer count register mn (TCRmn) is cleared to
0000H.
When the MDmn0 bit of the TMRmn register is 1,
INTTMmn is generated.
During
operation
Set values of only the CISmn1 and CISmn0 bits of the
TMRmn register can be changed.
The TDRmn register can always be read.
The TCRmn register can always be read.
The TSRmn register can always be read.
Set values of the TOMmn, TOLmn, TOmn, and TOEmn
bits cannot be changed.
Counter (TCRmn) counts up from 0000H. When the
valid edge of the TImn pin input is detected or the TSmn
bit is set to 1, the count value is transferred (captured) to
timer data register mn (TDRmn). At the same time, the
TCRmn register is cleared to 0000H, and the INTTMmn
signal is generated.
If an overflow occurs at this time, the OVF bit of timer
status register mn (TSRmn) is set; if an overflow does
not occur, the OVF bit is cleared.
After that, the above operation is repeated.
Operation
stop
The TTmn bit is set to 1.
The TTmn bit automatically returns to 0 because it is
a trigger bit.
TEmn = 0, and count operation stops.
The TCRmn register holds count value and stops.
The OVF bit of the TSRmn register is also held.
TAU
stop
The TAUmEN bit of the PER0 register is cleared to 0.
Input clock supply for timer array unit m is stopped
All circuits are initialized and SFR of each channel is
also initialized.
Summary of Contents for RL78/G1H
Page 941: ...R01UH0575EJ0120 RL78 G1H...
