CHAPTER 15 SERIAL INTERFACE IICA
Page 450 of 920
15.5
I
2
C Bus Definitions and Control Methods
The following section describes the I
2
C bus’s serial data communication format and the signals used by the I
2
C bus.
Figure 15 - 19 shows the transfer timing for the “start condition”, “address”, “data”, and “stop condition” output via the
I
2
C bus’s serial data bus.
Figure 15 - 19 I
2
C Bus Serial Data Transfer Timing
The master device generates the start condition, slave address, and stop condition.
The acknowledge (ACK) can be generated by either the master or slave device (normally, it is output by the device
that receives 8-bit data).
The serial clock (SCLAn) is continuously output by the master device. However, in the slave device, the SCLAn pin
low level period can be extended and a wait can be inserted.
15.5.1
Start conditions
A start condition is met when the SCLAn pin is at high level and the SDAAn pin changes from high level to low
level. The start conditions for the SCLAn pin and SDAAn pin are signals that the master device generates to the
slave device when starting a serial transfer. When the device is used as a slave, start conditions can be detected.
Figure 15 - 20 Start Conditions
A start condition is output when bit 1 (STTn) of IICA control register n0 (IICCTLn0) is set (1) after a stop condition
has been detected (SPDn: Bit 0 of the IICA status register n (IICSn) = 1). When a start condition is detected, bit 1
(STDn) of the IICSn register is set (1).
Remark
n = 0, 1
SCLAn
SDAAn
1-7
8
9
1-8
9
1-8
9
Start condition
Stop condition
Address
Data
Data
R/W
ACK
ACK
ACK
SCLAn
SDAAn
H
Summary of Contents for RL78/G1H
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