CHAPTER 15 SERIAL INTERFACE IICA
Page 469 of 920
15.5.15 Cautions
(1) When STCENn = 0
Immediately after I
2
C operation is enabled (IICEn = 1), the bus communication status (IICBSYn = 1) is
recognized regardless of the actual bus status. When changing from a mode in which no stop condition has
been detected to a master device communication mode, first generate a stop condition to release the bus,
then perform master device communication.
When using multiple masters, it is not possible to perform master device communication when the bus has
not been released (when a stop condition has not been detected).
Use the following sequence for generating a stop condition.
<1> Set IICA control register n1 (IICCTLn1).
<2> Set bit 7 (IICEn) of IICA control register n0 (IICCTLn0) to 1.
<3> Set bit 0 (SPTn) of the IICCTLn0 register to 1.
(2) When STCENn = 1
Immediately after I
2
C operation is enabled (IICEn = 1), the bus released status (IICBSYn = 0) is recognized
regardless of the actual bus status. To generate the first start condition (STTn = 1), it is necessary to confirm
that the bus has been released, so as to not disturb other communications.
(3) If other I
2
C communications are already in progress
If I
2
C operation is enabled and the device participates in communication already in progress when the
SDAAn pin is low and the SCLAn pin is high, the macro of I
2
C recognizes that the SDAAn pin has gone low
(detects a start condition). If the value on the bus at this time can be recognized as an extension code, ACK
is returned, but this interferes with other I
2
C communications. To avoid this, start I
2
C in the following
sequence.
<1> Clear bit 4 (SPIEn) of the IICCTLn0 register to 0 to disable generation of an interrupt request signal
(INTIICAn) when the stop condition is detected.
<2> Set bit 7 (IICEn) of the IICCTLn0 register to 1 to enable the operation of I
2
C.
<3> Wait for detection of the start condition.
<4> Set bit 6 (LRELn) of the IICCTLn0 register to 1 before ACK is returned (4 to 72 f
MCK
clocks after
setting the IICEn bit to 1), to forcibly disable detection.
(4) Setting the STTn and SPTn bits (bits 1 and 0 of the IICCTLn0 register) again after they are set and before
they are cleared to 0 is prohibited.
(5) When transmission is reserved, set the SPIEn bit (bit 4 of the IICCTLn0 register) to 1 so that an interrupt
request is generated when the stop condition is detected. Transfer is started when communication data is
written to the IICA shift register n (IICAn) after the interrupt request is generated. Unless the interrupt is
generated when the stop condition is detected, the device stops in the wait state because the interrupt
request is not generated when communication is started. However, it is not necessary to set the SPIEn bit to
1 when the MSTSn bit (bit 7 of the IICA status register n (IICSn)) is detected by software.
Remark
n = 0, 1
Summary of Contents for RL78/G1H
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