CHAPTER 15 SERIAL INTERFACE IICA
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The meanings of <1> to <7> in (1) Start condition ~ address ~ data in Figure 15 - 44 are explained below.
<1> The start condition trigger is set by the master device (STTn = 1) and a start condition (i.e. SCLAn =1 changes
SDAAn from 1 to 0) is generated once the bus data line goes low (SDAAn). When the start condition is
subsequently detected, the master device enters the master device communication status (MSTSn = 1). The
master device is ready to communicate once the bus clock line goes low (SCLAn = 0) after the hold time has
elapsed.
<2> The master device writes the address + R (reception) to the IICA shift register n (IICAn) and transmits the slave
address.
<3> In the slave device if the address received matches the address (SVAn value) of a slave device
, that slave
device sends an ACK by hardware to the master device. The ACK is detected by the master device (ACKDn =
1) at the rising edge of the 9th clock.
<4> The master device issues an interrupt (INTIICAn: end of address transmission) at the falling edge of the 9th
clock. The slave device whose address matched the transmitted slave address sets a wait status (SCLAn = 0)
and issues an interrupt (INTIICAn: address match)
<5> The timing at which the master device sets the wait status changes to the 8th clock (WTIMn = 0).
<6> The slave device writes the data to transmit to the IICAn register and releases the wait status that it set by the
slave device.
<7> The master device releases the wait status (WRELn = 1) and starts transferring data from the slave device to
the master device.
Note
If the transmitted address does not match the address of the slave device, the slave device does not
return an ACK to the master device (NACK: SDAAn = 1). The slave device also does not issue the
INTIICAn interrupt (address match) and does not set a wait status. The master device, however, issues
the INTIICAn interrupt (end of address transmission) regardless of whether it receives an ACK or
NACK.
Remark 1.
<1> to <19> in Figures 15 - 44 to 15 - 46 represent the entire procedure for communicating data
using the I
2
C bus. Figure 15 - 44 (1) Start condition ~ address ~ data shows the processing from
<1> to <7>, Figure 15 - 45 (2) Address ~ data ~ data shows the processing from <3> to <12>, and
Figure 15 - 46 (3) Data ~ data ~ stop condition shows the processing from <8> to <19>.
Remark 2.
n = 0, 1
Summary of Contents for RL78/G1H
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