CHAPTER 22 POWER-ON-RESET CIRCUIT
Page 759 of 920
Figure 22 - 4 Timing of Generation of Internal Reset Signal by Power-on-reset Circuit and Voltage Detector (3/3)
(3) LVD reset mode (option byte 000C1H: LVIMDS1, LVIMDS0 = 1, 1)
Note 1.
The internal reset processing time includes the oscillation accuracy stabilization time of the high-speed on-chip
oscillator clock.
Note 2.
The high-speed on-chip oscillator clock and a high-speed system clock or subsystem clock can be selected as the
CPU clock. To use the X1 clock, use the oscillation stabilization time counter status register (OSTC) to confirm the
lapse of the oscillation stabilization time. To use the XT1 clock, use the timer function for confirmation of the lapse of
the stabilization time.
Note 3.
The time until normal operation starts includes the following LVD reset processing time after the LVD detection level
(V
LVD
) is reached as well as the voltage stabilization wait + POR reset processing time after the V
POR
(1.51 V, TYP.) is
reached.
LVD reset processing time: 0 ms to 0.0701 ms (MAX.)
Note 4.
When the power supply voltage is below the lower limit for operation and the power supply voltage is then restored
after an internal reset is generated only by the voltage detector (LVD), the following LVD reset processing time is
required after the LVD detection level (V
LVD
) is reached.
LVD reset processing time: 0.0511 ms (TYP.), 0.0701 ms (MAX.)
Remark 1.
V
LVDH
, V
LVDL
: LVD detection voltage
V
POR
:
POR power supply rise detection voltage
V
PDR
:
POR power supply fall detection voltage
Remark 2.
When the LVD interrupt mode is selected (option byte 000C1H: LVIMD1 = 0, LVIMD0 = 1), the time until normal
operation starts after power is turned on is the same as the time specified in Note 3 of Figure 22 - 4 (3).
Supply voltage (V
DD
)
V
POR
= 1.51 V (TYP.)
V
PDR
= 1.50 V (TYP.)
Operating voltage range lower limit
0 V
Internal reset signal
High-speed on-chip
oscillator clock (f
IH
)
High-speed
system clock (f
MX
)
(when X1 oscillation
is selected)
V
LVD
Normal operation
Note 2
(high-speed on-chip
oscillator clock)
Wait for oscillation accuracy
stabilization
Note 1
Wait for oscillation
accuracy stabilization
Note 1
Reset
period
(oscillation
stop)
LVD reset processing time
Note 4
Voltage stabilization wait time + POR reset
processing time: 1.64 ms (TYP.), 3.10 ms (MAX.)
LVD reset processing time
Note 3
Starting oscillation is
specified by software
Starting oscillation is
specified by software
Normal operation
Note 2
(high-speed on-chip
oscillator clock)
Operation
stops
CPU
Reset period
(oscillation stop)
Summary of Contents for RL78/G1H
Page 941: ...R01UH0575EJ0120 RL78 G1H...
