CHAPTER 23 VOLTAGE DETECTOR
Page 763 of 920
23.3.2
Voltage detection level register (LVIS)
This register selects the voltage detection level.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation input sets this register to 00H/01H/81H
.
Figure 23 - 3 Format of Voltage detection level register (LVIS)
Note 1.
The reset value changes depending on the reset source and the setting of the option byte.
This register is not cleared (00H) by LVD reset.
The generation of reset signal other than an LVD reset sets as follows.
•
When option byte LVIMDS1, LVIMDS0 = 1, 0: 00H
•
When option byte LVIMDS1, LVIMDS0 = 1, 1: 81H
•
When option byte LVIMDS1, LVIMDS0 = 0, 1: 01H
Note 2.
Writing “0” can only be allowed in the interrupt & reset mode (option byte LVIMDS1, LVIMDS0 = 1, 0). Do not
set LVIMD and LVILV in other cases. The value is switched automatically when reset or interrupt is generated
in the interrupt & reset mode.
Caution 1. Rewrite the value of the LVIS register according to Figures 23 - 8.
Caution 2. Specify the LVD operation mode and detection voltage (V
LVDH
, V
LVDL
, V
LVD
) of each mode by using the
option byte 000C1H. For details about the user option byte, see CHAPTER 26 OPTION BYTE.
After reset:00H/01H/81H
Symbol
<7>
6
5
4
3
2
1
<0>
LVIS LVIMD
0
0
0
0
0
0
LVIMD
Operation mode of voltage detection
0
Interrupt mode
1
Reset mode
LVD detection level
0
High-voltage detection level (V
LVDH
)
1
Low-voltage detection level (V
LVDL
or V
LVD
)
Summary of Contents for RL78/G1H
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