CHAPTER 31 ELECTRICAL SPECIFICATIONS
Page 880 of 920
Note 1.
Use it with V
DD
≥
V
b
.
Note 2.
The maximum operating frequencies of the CPU/peripheral hardware clock (f
CLK
) are:
HS (high-speed main) mode: 32 MHz (2.7 V
≤
V
DD
≤
3.6 V)
16 MHz (2.4 V
≤
V
DD
≤
3.6 V)
LS (low-speed main) mode: 8 MHz (1.8 V
≤
V
DD
≤
3.6 V)
Caution
Select the TTL input buffer for the RxDq pin and the N-ch open drain output (V
DD
tolerance) mode for the TxDq
pin by using port input mode register g (PIMg) and port output mode register g (POMg). For V
IH
and V
IL
, see the
DC characteristics with TTL input buffer selected.
Remark 1.
V
b
[V]: Communication line voltage
Remark 2.
q: UART number (q = 1, 3), g: PIM and POM number (g = 0, 14)
Remark 3.
f
MCK
: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 02, 03, 12, 13))
(5) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode)
(T
A
=
‒
40 to +85
°
C, 1.8 V
≤
V
DD
≤
3.6 V, V
SS
= 0 V)
Parameter
Symbol
Conditions
HS (high-speed main)
mode
LS (low-speed main)
mode
Unit
MIN.
MAX.
MIN.
MAX.
Transfer rate
reception
2.7 V
≤
V
DD
<
3.6 V,
2.3 V
≤
Vb
≤
2.7 V
f
MCK
/6
f
MCK
/6
bps
Theoretical value of the
maximum transfer rate
f
MCK
= f
CLK
5.3
1.3
Mbps
1.8 V
≤
V
DD
<
3.3 V,
1.8 V
≤
Vb
≤
2.0 V
f
MCK
/6
f
MCK
/6
bps
Theoretical value of the
maximum transfer rate
f
MCK
= f
CLK
5.3
1.3
Mbps
(1/2)
Summary of Contents for RL78/G1H
Page 941: ...R01UH0575EJ0120 RL78 G1H...
