CHAPTER 7 TIMER ARRAY UNIT
Page 164 of 920
7.3.8
Timer input select register 0 (TIS0)
The TIS0 register is used to select the channels 0 and 1 of unit 0 timer input.
The TIS0 register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 7 - 20 Format of Timer input select register 0 (TIS0)
Caution 1. At least 1/f
MCK
+ 10 ns is necessary as the high-level and low-level widths of the timer input to be
selected. Thus, the TIS02 bit cannot be set to 1 when f
SUB
is selected as f
CLK
(CSS in CKC register =
1).
Caution 2. When selecting an event input signal from the ELC using timer input select register 0 (TIS0), select
f
CLK
using timer clock select register 0 (TPS0).
Address: F0074H
After reset: 00H
Symbol
7
6
5
4
3
2
1
0
0
0
0
TIS04
0
TIS02
TIS01
TIS00
Selection of timer input used with channel 0
0
No timer input
1
Event input signal from ELC
Selection of timer input used with channel 1
0
0
0
No timer input
0
0
1
Event input signal from ELC
1
0
0
Low-speed on-chip oscillator clock (f
IL
)
1
0
1
Subsystem clock (f
SUB
)
Other than above
Setting prohibited
Summary of Contents for RL78/G1H
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