R01UH0823EJ0100 Rev.1.00
Page 1089 of 1823
Jul 31, 2019
RX23W Group
33. Serial Communications Interface (SCIg, SCIh)
33.10.7
Selectable Timing for Sampling Data Received through RXDX12
The extended serial mode control section provides a way of adjusting the timing for the sampling of data received
through the RXDX12 pin by setting the CR2.RTS[1:0] bits to select the rising edges of 8th, 10th, 12th, or 14th cycle of
the base clock. If the value of the SEMR.ABCS bit is 1, the bits select the rising edges of 4th, 5th, 6th, or 7th cycle of the
base clock.
shows timing for the sampling of data received through RXDX12.
Figure 33.72
Timing for Sampling of Data Received through RXDX12
16 clocks
Base clock
RTS[1:0] = 00b
RXDX12 receive data
RTS[1:0] = 01b
RTS[1:0] = 10b
RTS[1:0] = 11b
8 clocks
The above diagram assumes the following:
SEMR.ABCS = 0
10 clocks
12 clocks
14 clocks
