R01UH0823EJ0100 Rev.1.00
Page 1166 of 1823
Jul 31, 2019
RX23W Group
35. I
2
C-bus Interface (RIICa)
35.7.2
Detection of the General Call Address
The RIIC has a facility for detecting the general call address (0000 000b + 0 (write)). This is enabled by setting the
ICSER.GCAE bit to 1.
If the address received after a start or restart condition is issued is 0000 000b + 1 (read) (start byte), the RIIC recognizes
this as the address of a slave device with an “all-zero” address but not as the general call address.
When the RIIC detects the general call address, both the ICSR1.GCA flag and the ICSR2.RDRF flag are set to 1 on the
rising edge of the ninth cycle of SCL clock. This leads to the generation of a receive data full interrupt (RXI). The value
of the GCA flag can be confirmed to recognize that the general call address has been transmitted.
Operation after detection of the general call address is the same as normal slave receive operation.
Figure 35.27
Timing of GCA Flag Setting during Reception of General Call Address
AAS2
AAS0
S
2
3
4
5
6
7
0
0
0
0
0
0
1
AAS1
9
ACK
BBSY
RDRF
2
3
4
5
6
7
8
9
ACK
1
General call address match (0000 000b + W)
[General call address reception]
1
0
GCA
8
W
2
3
4
5
Read ICDRR register
(Dummy read [7-bit address])
Read ICDRR register
(DATA 1)
Data (DATA 1)
Data (DATA 2)
Receive data (7-bit address)
Receive data (DATA 1)
SCL0
SDA0
