R01UH0823EJ0100 Rev.1.00
Page 1183 of 1823
Jul 31, 2019
RX23W Group
35. I
2
C-bus Interface (RIICa)
35.11.3
RIIC Reset and Internal Reset
The RIIC module incorporates a function for resetting itself. There are two types of reset. One is referred to as an RIIC
reset; this initializes all registers including the ICCR2.BBSY flag. The other is referred to as an internal reset; this
releases the RIIC from the slave-address matched state and initializes the internal counter while retaining other settings.
After issuing a reset, be sure to set the ICCR1.IICRST bit to 0.
Both types of reset are effective for release from bus-hung states because both restore the output state of the SCL0 and
SDA0 pins to the high-impedance state.
Issuing a reset during slave operation may lead to a loss of synchronization between the master device clock and the
slave device clock, so avoided this where possible. Note that monitoring of the bus state, such as for the presence of a
start condition, is not possible during an RIIC reset (bits ICE and IICRST in the ICCR1 register are 01b).
For a detailed description of the RIIC and internal resets, refer to
section 35.14, Initialization of Registers and
