R01UH0823EJ0100 Rev.1.00
Page 214 of 1823
Jul 31, 2019
RX23W Group
10. Clock Frequency Accuracy Measurement Circuit (CAC)
10.2.3
CAC Control Register 2 (CACR2)
Note:
Set the CACR2 register when the CACR0.CFME bit is 0.
RPS Bit (Reference Signal Select)
This bit selects whether to use the CACREF pin input or an internal clock (internally generated signal) as the reference
signal.
RSCS[2:0]Bits (Measurement Reference Clock Select)
These bits select the clock source for generating the measurement reference clock.
RCDS[1:0]Bits (Measurement Reference Clock Frequency Division Ration Select)
These bits select the frequency division ratio of the measurement reference clock.
DFS[1:0]Bits (Digital Filter Select)
The setting of these bits enables or disables the digital filter and selects its sampling clock.
Address(es): 0008 B002h
b7
b6
b5
b4
b3
b2
b1
b0
DFS[1:0]
RCDS[1:0]
RSCS[2:0]
RPS
Value after reset:
0
0
0
0
0
0
0
0
Bit
Symbol
Bit Name
Description
R/W
b0
Reference Signal Select
0: CACREF pin input
1: Internal clock (internally generated signal)
R/W
b3 to b1
Measurement Reference Clock
Select
b3 b1
0 0 0: Main clock
0 0 1: Sub-clock
0 1 0: HOCO clock
0 1 1: LOCO clock
1 0 0: IWDT-dedicated clock (IWDTCLK)
1 0 1: Peripheral module clock B (PCLKB)
Settings other than above are prohibited.
R/W
b5, b4
Measurement Reference Clock
Frequency Division Ration Select
b5 b4
0 0: ×1/32 clock
0 1: ×1/128 clock
1 0: ×1/1024 clock
1 1: ×1/8192 clock
R/W
b7, b6
Digital Filter Select
b7 b6
0 0: Digital filtering is disabled.
0 1: The sampling clock for the digital filter is the
measurement target clock.
1 0: The sampling clock for the digital filter is the
measurement target clock divided by 4.
1 1: The sampling clock for the digital filter is the
measurement target clock divided by 16.
R/W
