R01UH0823EJ0100 Rev.1.00
Page 376 of 1823
Jul 31, 2019
RX23W Group
18. DMA Controller (DMACA)
Specifically, the different procedures are used for canceling an interrupt to restart DMA transfer in the following two
cases: (1) discontinuing or terminating DMA transfer and (2) continuing DMA transfer.
(1) When Discontinuing or Terminating DMA Transfer
Write 0 to the DTIF bit in DMSTS of DMACm to clear a transfer end interrupt, and to the ESIF bit in DMSTS of
DMACm to clear a repeat size interrupt and an extended repeat area overflow interrupt. The DMACm remains in the
stop state. When starting another DMA transfer after that, set the appropriate registers, and set the DTE bit in DMCNT of
DMACm to 1 (DMA transfer enabled).
(2) When Continuing DMA Transfer
Write 1 to the DTE bit in DMCNT of DMACm. The ESIF bit in DMSTS of DMACm is automatically cleared to 0
(interrupt source cleared), and DMA transfer is resumed.
Figure 18.14
DMAC Interrupt Handling Routine to Resume/Terminate DMA Transfer
18.6
Event Link Function
Each DMAC channel outputs an event link request signal each time the channel completes data transfer (or block transfer
in block transfer mode). However, when the transfer destination is the internal peripheral bus, an event link request
signal is generated when the write to the write buffer is accepted.
Start of DMAC interrupt
handling
Write 1 to DTE bit in DMACm.DMCNT.
Write 0 to ESIF or DTIF bit in DMACm.DMSTS.
(Interrupt source cleared)
Write 1 to DTE bit in DMACm.DMCNT.
DMA transfer restarted
(Start of another DMA transfer)
Transfer resumed
ESIF bit in DMACm.DMSTS cleared automatically.
(Interrupt source cleared)
Change register settings if necessary.
Change register settings.
Interrupt request from DMAC
Is suspended transfer
continued?
Continue
Terminate
End
Is another data transfer
performed?
Start another transfer
Discontinue
