R01UH0823EJ0100 Rev.1.00
Page 396 of 1823
Jul 31, 2019
RX23W Group
19. Data Transfer Controller (DTCa)
19.4.4
Repeat Transfer Mode
This mode allows 1-byte, 1-word, or 1-longword data transfer on a single transfer request.
Specify either transfer source or transfer destination for the repeat area by the MRB.DTS bit. The transfer count can be
set to 1 to 256. When the specified-count transfer is completed, the initial value of the address register specified in the
transfer counter and the repeat area is restored and transfer is repeated. The other address register is incremented or
decremented continuously or remains unchanged.
When the transfer counter CRAL is decreased to 00h in repeat transfer mode, the CRAL value is updated to the value set
in the CRAH register. Thus the transfer counter does not become 00h, which disables an interrupt request to be generated
to the CPU when the MRB.DISEL bit is set to 0 (an interrupt request to the CPU is generated on completion of the
specified number of data transfers).
lists the register functions in repeat transfer mode, and
shows the memory map of repeat
transfer mode.
Note 1. Write-back operation is skipped when address is fixed.
Figure 19.6
Memory Map of Repeat Transfer Mode (Transfer Source: Repeat Area)
Table 19.6
Register Functions in Repeat Transfer Mode
Register
Description
Value Written Back by Writing Transfer Information
When CRAL ≠ 1
When CRAL = 1
When the MRB.DTS Bit is 0
When the MRB.DTS Bit is 1
SAR
Transfer source address
Increment/decrement/fixed*
Increment/decrement/fixed*
SAR register initial value
DAR
Transfer destination
address
Increment/decrement/fixed*
DAR register initial value
Increment/decrement/fixed*
Retains initial value of
transfer counter
Transfer counter A
CRB
Transfer counter B
Not updated
Not updated
SAR
Transfer source data area
(set to repeat area)
DAR
Transfer
Transfer destination data area
Data 1
Data 2
Data 3
Data 4
Data 1
Data 2
Data 3
Data 4
Data 1
Data 2
Data 3
Data 4
