R01UH0823EJ0100 Rev.1.00
Page 531 of 1823
Jul 31, 2019
RX23W Group
23. Multi-Function Timer Pulse Unit 2 (MTU2a)
23.3.4
Cascaded Operation
In cascaded operation, 16-bit counters in different two channels are used together as a 32-bit counter.
This function works when overflow/underflow of the MTU2.TCNT counter is selected as the count clock for MTU1
through the TCR.TPSC[2:0] bits.
Underflow occurs only when the lower 16 bits of the TCNT counter is in phase counting mode.
lists the register combinations used in cascaded operation.
Note:
When phase counting mode is set for MTU1 or MTU2, the count clock setting is invalid and the counters operate
independently in phase counting mode.
For simultaneous input capture of MTU1.TCNT and MTU2.TCNT during cascaded operation, additional input capture
input pins can be specified by the TICCR register. The input-capture condition is of edges in the signal produced by
taking the logical OR of the input level on the main input pin and the input level on the added input pin. Accordingly, if
either is at the high, a change in the level of the other will not produce an edge for detection. For details, refer to
Cascaded Operation Example (c)
. For input capture in cascade connection, refer to
Input Capture in MTU1.TCNT and MTU2.TCNT in Cascade Connection
lists the TICCR setting and input capture input pins.
Table 23.41
Cascaded Combinations
Combination
Upper 16 Bits
Lower 16 Bits
MTU1 and MTU2
MTU1.TCNT
MTU2.TCNT
Table 23.42
TICCR Setting and Input Capture Input Pins
Target Input Capture
TICCR Setting
Input Capture Input Pin
Input capture from MTU1.TCNT to
MTU1.TGRA
I2AE bit = 0 (initial value)
MTIOC1A
I2AE bit = 1
MTIOC1A, MTIOC2A
Input capture from MTU1.TCNT to
MTU1.TGRB
I2BE bit = 0 (initial value)
MTIOC1B
I2BE bit = 1
MTIOC1B, MTIOC2B
Input capture from MTU2.TCNT to
MTU2.TGRA
I1AE bit = 0 (initial value)
MTIOC2A
I1AE bit = 1
MTIOC2A, MTIOC1A
Input capture from MTU2.TCNT to
MTU2.TGRB
I1BE bit = 0 (initial value)
MTIOC2B
I1BE bit = 1
MTIOC2B, MTIOC1B
