RFL 9785
RFL Electronics Inc.
July 26, 2007
16-6
(973) 334-3100
16.4.3
SERIAL PORT OPERATION
DUART U1 and its associated components control all RS-232 communications. U1 handles baud-rate
generation, data formatting, handshaking, and Tx and Rx buffering so that a considerable burden is
removed from the CPU. In addition, it provides a 9600-Hz clock on output line OP3, which is used for
the shift register clock (SRCLK).
U1 occupies locations 4000H through 400FH on the memory-map. As such, the CPU handles
read/write operations as though it were simply a RAM.
The serial data to/from the DUART is sent through the motherboard to the SOE Module. All user
interface with the Checkback Module is performed through the SOE Module in the 9785 chassis. The
connection between the two modules uses raw logic levels, rather than converting to RS-232 and back
again. The RS-232 interface device (U4) is not utilized when the Checkback Module is used in a 9785
chassis.
16.4.4
EXTERNAL INPUTS
External inputs are interfaced to the RFL 9785 through DUART U1. All external inputs are provided
with pull-up/down resistors, and RC noise filtering. After filtering, the inputs are connected to U1’s
input lines IP1 through IP6.
When the CPU is ready to read input status, it enables U1 using address 400DH. The Read (/RD) line
is pulled low, and the CPU places the status information on lines AD0 through AD7. When the bus has
stabilized, the CPU reads the status in, and the sequence is completed.
16.4.5
CPU OUTPUTS
U2 is an XILINX XC95108 high-performance CPLD (Complex Programmable Logic Device) which is
used to interface the Checkback outputs. The XC95108 is programmed as an address decoder, address
latch, display latches and drivers, relay latches and drivers, shift register, flip-flops and logic gates.
This includes 33 LED control lines, two status signals, and two lines which are used to drive
MOSFETs Q1 and Q2 which drive the Test In Process (TIP) and Test Out relays.
